djzenma / rv32ic-cpu

Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.

RV32IC-CPU

Implementation of the RV32IC Processor in Verilog HDL

Directories

The Repository contains the following Directories:

RTL

Contains all the verilog implementations

Test

Contains the testCase.txt file where you can put your own testcases (assembly instructions), and contains a simulation configuration file that you can use to see a nice looking simulation.

Reports

Contains a full detailed documentation about the CPU implementation.

Test it yourself!

If you want to test your own code on my RISCV32IC CPU, please do the following:
1. convert your code to hex,
2. then go to the file “RTL/TestBench/testCase.txt” in the project directory and paste your code into it.
3. Please make sure to change the path of the "testCase.txt" file in the $readmemh() function in the Memory module according to your own path.