djswain9 / neumann_fpga

FPGA emulation for project neumann.

Project Neumann

Project Neumann is a RISC-V based microcontroller system using the PULPino core from the PULP platform with an 12-bit SAR ADC, internal clock and other analog and digital peripherals to build complete embedded solutions.

FPGA developement for functionality test

Resources

• PULP: Joint effort between ETH Zurich and U. of Bologna for effcient architectures for Ultra Low Power application.
• PULPino: Single-core microcontroller system using RISCY or zero-riscy.
• Rocket Chip: Free RISC-V core generator maintained by UC Berkeley.
• SiFive: company formed by the original inventors of RISC-V.

References

1. Gautschi, M., P. D. Schiavone, A. Traber, I. Loi, A. Pullini, D. Rossi, E. Flamand, F. K. Gürkaynak, and L. Benini. “Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices.” IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 10 (October 2017): 2700–2713. https://doi.org/10.1109/TVLSI.2017.2654506. [ PVu ]
2. Schiavone, P. Davide, F. Conti, D. Rossi, M. Gautschi, A. Pullini, E. Flamand, and L. Benini. “Slow and Steady Wins the Race? A Comparison of Ultra-Low-Power RISC-V Cores for Internet-of-Things Applications.” In 2017 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 1–8, 2017. https://doi.org/10.1109/PATMOS.2017.8106976. [ PVu ]

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