djswain9 / 1-bit-full-adder

This repository presents the design and implementation of a 1-Bit Full Adder circuit using 28 CMOS technology. Implementation and simulation are done using the Synopsis tool only. For the representation of inputs and outputs, we have taken the voltage range 0v to 1.8v. The truth table of the 1- Bit Full Adder is verified by the waveform obtained from the simulation. A full adder can be designed using two Half adders but this design is a little modified version with less no of MOSFETs.

I'm Debarchan

A 4th year student pursuing my Bachelors’s in Electronics and Communication Engineering,
from Silicon Institute of Technology,Bhubaneswar.
I am a VLSI,Linux and IoT enthusiast.

• 🔭 I’m currently working on my skills.

• 💬 Ask me about VLSI and LINUX.

• 🌱 I’m currently learning PYTHON and VLSI.

• 📫 Contact me here: [email protected]

My Github Stats

Note: Top languages is only a metric of the languages my public code consists of and doesn't reflect experience or skill level.