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Automatically exported from code.google.com/p/idlab-scrod
In packet_builder, the window does not seem to increment properly for row 0,
col 0, ch 0. Other windows seem okay, but this one is always(?) behind by one?
Original issue reported on code.google.com by mzandrew
on 12 Nov 2011 at 10:28
This occurs when the board is powered and programmed and chipscope is opened,
or when the "update all" button of chipscope is used to set all DAC values.
The state machine appears to acknowledge and the "current" DAC values all
update appropriately, but probing on the board indicates not all values were
truly accepted.
Original issue reported on code.google.com by [email protected]
on 12 Jul 2011 at 10:06
the transceiver requires a remove/insert cycle sometimes instead of respecting
the DISABLE powerdown signal
Original issue reported on code.google.com by mzandrew
on 19 Jul 2011 at 6:02
Modules seem to double trigger and/or miss fiber commands altogether. (A
front-end veto has been added, but causes the DAQ to sometimes stall when in
software trigger mode. This implies to me that commands are definitely being
dropped/missed.)
=possible aid in debugging:=
Have event header or footer report back the number of unrecognized / improperly
formatted commands.
Original issue reported on code.google.com by mzandrew
on 12 Nov 2011 at 10:31
During normal running, the write address logic decoding enable, denoted
WR_ADDR(9), should be high for 4 cycles of SST, corresponding to 8 total
windows written.
It seems to be unstable, sometimes giving one extra cycle of enable. This may
or may not be related to the stale data seen in the first window.
Original issue reported on code.google.com by [email protected]
on 12 Jul 2011 at 10:03
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