diqiuren / idlab-scrod Goto Github PK

In packet_builder, the window does not seem to increment properly for row 0, 
col 0, ch 0.  Other windows seem okay, but this one is always(?) behind by one? 

This occurs when the board is powered and programmed and chipscope is opened, 
or when the "update all" button of chipscope is used to set all DAC values.

The state machine appears to acknowledge and the "current" DAC values all 
update appropriately, but probing on the board indicates not all values were 
truly accepted.

the transceiver requires a remove/insert cycle sometimes instead of respecting 
the DISABLE powerdown signal

Modules seem to double trigger and/or miss fiber commands altogether.  (A 
front-end veto has been added, but causes the DAQ to sometimes stall when in 
software trigger mode.  This implies to me that commands are definitely being 
dropped/missed.)

=possible aid in debugging:=
Have event header or footer report back the number of unrecognized / improperly 
formatted commands.

During normal running, the write address logic decoding enable, denoted 
WR_ADDR(9), should be high for 4 cycles of SST, corresponding to 8 total 
windows written.

It seems to be unstable, sometimes giving one extra cycle of enable.  This may 
or may not be related to the stale data seen in the first window.