I'm trying to get the ADC1410 to work in the Eclypse Z7 FPGA board with a verilog-pure program, making use of the IP Core provided by Digilent (ZmodADC1410_Controller).
Up to now, I'am reading trash data from the IP output, so I suppose I've made a mistake in the connections or in the data acquisition or something else.
I've not seen any example of a verilog instantiation of the IP, so please let me know if there's any out there.
The IP instantiation is the simplest one: without dinamic calibration or SPI commands.
I'm reading convertions at ADC's system clock posedge.
/* TOP */
module top
(
input i_reset, /* onboard button */
input i_clock, /* 125 MHz onboard */
output o_tx, /* uart output */
output syzygy_d_n_0, /* sc1_ac_l */
output syzygy_d_p_0, /* sc1_ac_h */
output syzygy_d_n_1, /* sc2_ac_l */
output syzygy_d_p_1, /* sc2_ac_h */
output syzygy_d_n_2, /* sclk_sc */
inout syzygy_d_p_2, /* sdio_sc */
output syzygy_d_n_3, /* sc2_gain_l */
output syzygy_d_p_3, /* sc2_gain_h */
input syzygy_d_n_4, /* data 2 */
input syzygy_d_p_4, /* data 9 */
output syzygy_d_n_5, /* sc1_gain_l */
output syzygy_d_p_5, /* sc1_gain_h */
input syzygy_d_n_6, /* data 4 */
input syzygy_d_p_6, /* data 3 */
output syzygy_d_n_7, /* com_sc_l */
output syzygy_d_p_7, /* com_sc_h */
input syzygy_s_16, /* data 5 */
input syzygy_s_17, /* data 8 */
input syzygy_s_18, /* data 6 */
input syzygy_s_19, /* data 10 */
input syzygy_s_20, /* data 7 */
input syzygy_s_21, /* data 11 */
input syzygy_s_22, /* data 1 */
input syzygy_s_23, /* data 12 */
input syzygy_s_24, /* data 0 */
input syzygy_s_25, /* data 13 */
output syzygy_s_26, /* cs_sc1n */
output syzygy_s_27, /* sync_adc */
output syzygy_c2p_clk_n, /* adc clock in n */
output syzygy_c2p_clk_p, /* adc clock in p */
input syzygy_p2c_clk_p, /* clkout adc */
output syzygy_p2c_clk_n /* GND */
);
/* System */
wire clock;
wire locked;
/* ADC */
localparam ADC_DATA_OUT_SIZE = 16;
localparam ADC_DATA_IN_SIZE = 14;
wire adc_init_done;
wire adc_clock;
wire [ ADC_DATA_OUT_SIZE - 1 : 0 ] adc_data_out_ch1;
wire [ ADC_DATA_OUT_SIZE - 1 : 0 ] adc_data_out_ch2;
wire [ ADC_DATA_IN_SIZE - 1 : 0 ] adc_data_in;
wire adc_test_mode;
wire adc_fifo_empty_ch1;
wire adc_fifo_empty_ch2;
integer adc_data_count;
assign syzygy_p2c_clk_n = 1'b0;
assign adc_test_mode = 1'b0;
assign adc_data_in[ 0 ] = syzygy_s_24;
assign adc_data_in[ 1 ] = syzygy_s_22;
assign adc_data_in[ 2 ] = syzygy_d_n_4;
assign adc_data_in[ 3 ] = syzygy_d_p_6;
assign adc_data_in[ 4 ] = syzygy_d_n_6;
assign adc_data_in[ 5 ] = syzygy_s_16;
assign adc_data_in[ 6 ] = syzygy_s_18;
assign adc_data_in[ 7 ] = syzygy_s_20;
assign adc_data_in[ 8 ] = syzygy_s_17;
assign adc_data_in[ 9 ] = syzygy_d_p_4;
assign adc_data_in[ 10 ] = syzygy_s_19;
assign adc_data_in[ 11 ] = syzygy_s_21;
assign adc_data_in[ 12 ] = syzygy_s_23;
assign adc_data_in[ 13 ] = syzygy_s_25;
/* ###################################### */
clk_wiz_0
u_clk_wiz_0
(
.clk_in1 (i_clock),
.reset (i_reset),
.clk_out1 (clock), /* sys clock: 100MHz */
.clk_out2 (adc_clock), /* adc clock: 400MHz */
.locked (locked)
);
/* ###################################### */
ZmodADC1410_Controller_0
u_ZmodADC1410_Controller_0
(
.SysClk (clock), // IN STD_LOGIC;
.ADC_InClk (adc_clock), // IN STD_LOGIC;
.sRst_n (locked), // IN STD_LOGIC;
.sInitDone_n (adc_init_done), // OUT STD_LOGIC;
.FIFO_EMPTY_CHA (adc_fifo_empty_ch1), // OUT STD_LOGIC;
.FIFO_EMPTY_CHB (adc_fifo_empty_ch2), // OUT STD_LOGIC;
.sCh1Out (adc_data_out_ch1), // OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
.sCh2Out (adc_data_out_ch2), // OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
.sTestMode (adc_test_mode), // IN STD_LOGIC;
.adcClkIn_p (syzygy_c2p_clk_p), // OUT STD_LOGIC;
.adcClkIn_n (syzygy_c2p_clk_n), // OUT STD_LOGIC;
.adcSync (syzygy_s_27), // OUT STD_LOGIC;
.DcoClk (syzygy_p2c_clk_p), // IN STD_LOGIC;
.dADC_Data (adc_data_in), // IN STD_LOGIC_VECTOR(13 DOWNTO 0);
.sADC_SDIO (syzygy_d_p_2), // INOUT STD_LOGIC;
.sADC_CS (syzygy_s_26), // OUT STD_LOGIC;
.sADC_Sclk (syzygy_d_n_2), // OUT STD_LOGIC;
.sCh1CouplingH (syzygy_d_p_0), // OUT STD_LOGIC;
.sCh1CouplingL (syzygy_d_n_0), // OUT STD_LOGIC;
.sCh2CouplingH (syzygy_d_p_1), // OUT STD_LOGIC;
.sCh2CouplingL (syzygy_d_n_1), // OUT STD_LOGIC;
.sCh1GainH (syzygy_d_p_5), // OUT STD_LOGIC;
.sCh1GainL (syzygy_d_n_5), // OUT STD_LOGIC;
.sCh2GainH (syzygy_d_p_3), // OUT STD_LOGIC;
.sCh2GainL (syzygy_d_n_3), // OUT STD_LOGIC;
.sRelayComH (syzygy_d_p_7), // OUT STD_LOGIC;
.sRelayComL (syzygy_d_n_7) // OUT STD_LOGIC
);
/* ###################################### */
endmodule
/* CONSTRAINT */
## 125MHz Clock from Ethernet PHY
set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { i_clock }]; #IO_L12P_T1_MRCC Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { i_clock }];
## Buttons
set_property -dict { PACKAGE_PIN C18 IOSTANDARD LVCMOS33 } [get_ports { i_reset }]; #IO_L11N_T1_SRCC Sch=btn[1]
## Syzygy Port A
set_property -dict { PACKAGE_PIN N20 IOSTANDARD DIFF_SSTL18_I } [get_ports { syzygy_c2p_clk_n }]; #IO_L14N_T2_SRCC Sch=syzygy_a_c2p_clk_n
set_property -dict { PACKAGE_PIN N19 IOSTANDARD DIFF_SSTL18_I } [get_ports { syzygy_c2p_clk_p }]; #IO_L14P_T2_SRCC Sch=syzygy_a_c2p_clk_p
set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_0 }]; #IO_L21N_T3_DQS Sch=syzygy_a_d_n[0]
set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_0 }]; #IO_L21P_T3_DQS Sch=syzygy_a_d_p[0]
set_property -dict { PACKAGE_PIN T19 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_1 }]; #IO_L22N_T3 Sch=syzygy_a_d_n[1]
set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_1 }]; #IO_L22P_T3 Sch=syzygy_a_d_p[1]
set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_2 }]; #IO_L23N_T3 Sch=syzygy_a_d_n[2]
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_2 }]; #IO_L23P_T3 Sch=syzygy_a_d_p[2]
set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_3 }]; #IO_L20N_T3 Sch=syzygy_a_d_n[3]
set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_3 }]; #IO_L20P_T3 Sch=syzygy_a_d_p[3]
set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_4 }]; #IO_L24N_T3 Sch=syzygy_a_d_n[4]
set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_4 }]; #IO_L24P_T3 Sch=syzygy_a_d_p[4]
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_5 }]; #IO_L19N_T3_VREF Sch=syzygy_a_d_n[5]
set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_5 }]; #IO_L19P_T3 Sch=syzygy_a_d_p[5]
set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_6 }]; #IO_L7N_T1 Sch=syzygy_a_d_n[6]
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_6 }]; #IO_L7P_T1 Sch=syzygy_a_d_p[6]
set_property -dict { PACKAGE_PIN K21 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_n_7 }]; #IO_L9N_T1_DQS Sch=syzygy_a_d_n[7]
set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS18 } [get_ports { syzygy_d_p_7 }]; #IO_L9P_T1_DQS Sch=syzygy_a_d_p[7]
set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS18 } [get_ports { syzygy_p2c_clk_n }]; #IO_L13N_T2_MRCC Sch=syzygy_a_p2c_clk_n
set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS18 } [get_ports { syzygy_p2c_clk_p }]; #IO_L13P_T2_MRCC Sch=syzygy_a_p2c_clk_p
set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_16 }]; #IO_L12N_T1_MRCC Sch=syzygy_a_s[16]
set_property -dict { PACKAGE_PIN K20 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_17 }]; #IO_L11N_T1_SRCC Sch=syzygy_a_s[17]
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_18 }]; #IO_L12P_T1_MRCC Sch=syzygy_a_s[18]
set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_19 }]; #IO_L11P_T1_SRCC Sch=syzygy_a_s[19]
set_property -dict { PACKAGE_PIN L22 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_20 }]; #IO_L10N_T1 Sch=syzygy_a_s[20]
set_property -dict { PACKAGE_PIN J22 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_21 }]; #IO_L8N_T1 Sch=syzygy_a_s[21]
set_property -dict { PACKAGE_PIN L21 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_22 }]; #IO_L10P_T1 Sch=syzygy_a_s[22]
set_property -dict { PACKAGE_PIN J21 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_23 }]; #IO_L8P_T1 Sch=syzygy_a_s[23]
set_property -dict { PACKAGE_PIN N22 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_24 }]; #IO_L16P_T2 Sch=syzygy_a_s[24]
set_property -dict { PACKAGE_PIN P22 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_25 }]; #IO_L16N_T2 Sch=syzygy_a_s[25]
set_property -dict { PACKAGE_PIN M21 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_26 }]; #IO_L15P_T2_DQS Sch=syzygy_a_s[26]
set_property -dict { PACKAGE_PIN M22 IOSTANDARD LVCMOS18 } [get_ports { syzygy_s_27 }]; #IO_L15N_T2_DQS Sch=syzygy_a_s[27]
Any help would be apreciated.