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View Code? Open in Web Editor NEWRust crate to interface with the STMicro HTS221 sensor
License: Apache License 2.0
Rust crate to interface with the STMicro HTS221 sensor
License: Apache License 2.0
#![deny(unsafe_code)]
#![no_main]
#![no_std]
extern crate stm32l4xx_hal;
extern crate hts221;
extern crate cortex_m;
#[macro_use(entry, exception)]
extern crate cortex_m_rt as rt;
#[macro_use(block)]
extern crate nb;
extern crate panic_semihosting;
use cortex_m_rt::entry;
use cortex_m_semihosting::{debug, hprintln};
use hts221::Builder;
use stm32l4xx_hal::rcc::RccExt;
use stm32l4xx_hal::gpio::GpioExt;
use stm32l4::stm32l4x5::interrupt;
use stm32l4xx_hal::i2c::SdaPin;
use stm32l4xx_hal::i2c::SclPin;
use stm32l4xx_hal::i2c::Error;
use stm32l4xx_hal::i2c::I2c;
use stm32l4xx_hal::stm32::I2C2;
use stm32l4xx_hal::flash::FlashExt;
use stm32l4xx_hal::time::U32Ext;
use stm32l4xx_hal::prelude::*;
use crate::stm32l4xx_hal::serial::Serial;
const PERIOD: u32 = 5_000_000;
#[entry]
fn main() -> ! {
//hprintln!("Hello, world!").unwrap();
let peripherals = stm32l4xx_hal::stm32l4::stm32l4x5::Peripherals::take().unwrap();
let mut flash = peripherals.FLASH.constrain();
let mut rcc = peripherals.RCC.constrain();
let mut gpiob = peripherals.GPIOB.split(&mut rcc.ahb2);
let clocks = rcc.cfgr.freeze(&mut flash.acr);
let tx = gpiob.pb6.into_af7(&mut gpiob.moder, &mut gpiob.afrl);
let rx = gpiob.pb7.into_af7(&mut gpiob.moder, &mut gpiob.afrl);
let serial = Serial::usart1( peripherals.USART1, (tx, rx), 115_200.bps(), clocks, &mut rcc.apb2);
let (mut tx, mut rx) = serial.split();
let sent = b'A';
block!(tx.write(sent)).ok();
//let p = stm32l4xx_hal::stm32l4::stm32l4x5::Peripherals::take().unwrap();
block!(tx.write(b'h')).ok();
let scl = gpiob.pb10.into_open_drain_output(&mut gpiob.moder, &mut gpiob.otyper).into_af4(&mut gpiob.moder, &mut gpiob.afrh);
let sda = gpiob.pb11.into_open_drain_output(&mut gpiob.moder, &mut gpiob.otyper).into_af4(&mut gpiob.moder, &mut gpiob.afrh);
block!(tx.write(b'k')).ok();
let i2c = I2c::i2c2(
peripherals.I2C2,
(scl,sda),
1.mhz(),
rcc.cfgr.freeze(&mut flash.acr),
&mut rcc.apb1r1
);
block!(tx.write(b'z')).ok();
let mut hts = hts221::Builder::new(i2c)
.with_avg_t(hts221::AvgT::Avg256)
.with_avg_h(hts221::AvgH::Avg512)
.build()
.unwrap();
let x = 4;//hts.temperature_x8().unwrap() / 8;
block!(tx.write(b'Y')).ok();
block!(tx.write(x as u8)).ok();
//hprintln!("temperature: {}",hts.temperature_x8().unwrap() / 8);
loop {}
}
I get runtime error, after this command block!(tx.write(b'k')).ok();
openocd :
Open On-Chip Debugger 0.10.0
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'.
Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
adapter speed: 500 kHz
adapter_nsrst_delay: 100
none separate
Info : Unable to match requested speed 500 kHz, using 480 kHz
Info : Unable to match requested speed 500 kHz, using 480 kHz
Info : clock speed 480 kHz
Info : STLINK v2 JTAG v28 API v2 SWIM v18 VID 0x0483 PID 0x374B
Info : using stlink api v2
Info : Target voltage: 3.242300
Info : stm32l4x.cpu: hardware has 6 breakpoints, 4 watchpoints
Info : accepting 'gdb' connection on tcp/3333
Info : device id = 0x10076415
Info : flash size = 1024kbytes
undefined debug reason 7 - target needs reset
Info : Unable to match requested speed 500 kHz, using 480 kHz
Info : Unable to match requested speed 500 kHz, using 480 kHz
adapter speed: 480 kHz
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x080097ca msp: 0x20018000
adapter speed: 4000 kHz
Info : Padding image section 0 with 20 bytes
target halted due to breakpoint, current mode: Thread
xPSR: 0x61000000 pc: 0x20000050 msp: 0x20018000
Warn : block write succeeded
Info : Unable to match requested speed 500 kHz, using 480 kHz
Info : Unable to match requested speed 500 kHz, using 480 kHz
adapter speed: 480 kHz
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x080097ca msp: 0x20018000
gdb session:
tasosxak@tasosxak:~/Documents/RustProjects/app$ cargo run --example hello
Finished dev [unoptimized + debuginfo] target(s) in 8.11s
Running `gdb-multiarch -q -x openocd.gdb target/thumbv7em-none-eabi/debug/examples/hello`
Reading symbols from target/thumbv7em-none-eabi/debug/examples/hello...done.
0x00000000 in ?? ()
Breakpoint 1 at 0x8009810: file /home/tasosxak/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rt-0.6.7/src/lib.rs,line 553.
Breakpoint 2 at 0x8009a1c: file /home/tasosxak/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rt-0.6.7/src/lib.rs,line 543.
Breakpoint 3 at 0x8008c2e: file /home/tasosxak/.cargo/registry/src/github.com-1ecc6299db9ec823/panic-semihosting-0.5.1/src/lib.rs, line 78.
Loading section .vector_table, size 0x188 lma 0x8000000
Loading section .text, size 0x98a4 lma 0x8000188
Loading section .rodata, size 0x1248 lma 0x8009a40
Start address 0x80097ca, load size 44148
Transfer rate: 33 KB/sec, 8829 bytes/write.
(gdb) break main
Breakpoint 4 at 0x800268e: file examples/hello.rs, line 39.
(gdb) continue
Continuing.
Note: automatically using hardware breakpoints for read-only addresses.
Breakpoint 4, main () at examples/hello.rs:39
39 let peripherals = stm32l4xx_hal::stm32l4::stm32l4x5::Peripherals::take().unwrap();
(gdb) continue
Continuing.
Breakpoint 3, rust_begin_unwind (info=0x20017dd4)
at /home/tasosxak/.cargo/registry/src/github.com-1ecc6299db9ec823/panic-semihosting-0.5.1/src/lib.rs:78
78 interrupt::disable();
(gdb)
minicom:
Welcome to minicom 2.7.1
OPTIONS: I18n
Compiled on Aug 13 2017, 15:25:34.
Port /dev/ttyACM0, 15:28:48
Press CTRL-A Z for help on special keys
Ahkz
Use embedded-hal traits to support both blocking and non-blocking SPI communication
If the rH% is less than 0 or greater than 100, we should return an error (which should include the erroneous value). Similarly for temperature, which has an operating range of -40 to 120 deg C.
The example snippets in the documentation do not compile. Update them so that they do.
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