daglem / redip-sid Goto Github PK

Hi!

I don't see any resistor in series for potX/Y, it means when pot is in lower resistivity state (~0 Ohm) with strong 5V drive and FPGA is pulling it down to GND then high current will flow. Isn't it dangerous for FPGA/level-shifter/4066?

Hello!
I'm trying to use dfu-util:

dfu-util.exe -d 1d50:6159,:6156 -a 0 -D redip_sid.bin -R
dfu-util 0.11

Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
Copyright 2010-2021 Tormod Volden and Stefan Schmidt
This program is Free Software and has ABSOLUTELY NO WARRANTY
Please report bugs to http://sourceforge.net/p/dfu-util/tickets/

Warning: Invalid DFU suffix signature
A valid DFU suffix will be required in a future dfu-util release
Opening DFU capable USB device...
Device ID 1d50:6159
Device DFU version 0101
Claiming USB DFU (Run-Time) Interface...
Setting Alternate Interface zero...
Determining device status...
Device does not implement get_status, assuming appIDLE
Device really in Run-Time Mode, send DFU detach request...
Device will detach and reattach...
Lost device after RESET?

reDIP-SID disappears from device manager and left in state with CDONE LED ON.

Hi!
I suggest to use A5 and A8 inputs as 8580/6581 modes switch when compiled as a single SID (SID2 not defined).

i propose change to these lines:

change it to:

    sid::cfg_t  sid1_cfg = {  cs.a5 ? sid::MOS8580 : sid::MOS6581, sid::D400, 9'd250, -11'sd384 };
    sid::cfg_t  sid2_cfg = { ~cs.a8 ? sid::MOS8580 : sid::MOS6581, sid::D400, 9'd250, -11'sd384 };

{A8,A5} will do:
11 - 8581+6580
01 - 2x6581
10 - 2x8580

So, if user will connect 3-positions switch to A8 and A5 with middle pin to GND, then in middle position it will be a mix of 6581 and 8580 and on side positions it will be either 6581 or 8580. Similar to SIDFX board.
in pcf file these pins need to be pulled up which shouldn't harm as pullup resistor is very weak (20K-100K). So it won't require external pullup resistors.

I believe 99% users will need this mode. Generic user just need to play games and thus simply need to switch between 6581 and 8580 in real time.

I've also added -384 fc_offset, so 6581 mode sounds more generic way like 6581R2/R3 (R4, R4AR are muffling IMHO).

If you want, i can make pull request with required changes.

Hi!

On schematics and BOM you've used CBT version with 5V TTL output, so you use voltage divider to get 4.3V which is probably still not good for FPGA. Why you are insisting on this particular version instead of CBTD or CB3T versions providing correct 3.3V level shifting?

Hi!

in readme you wrote:

All FPGA I/O is 5V tolerant, and can drive 5V TTL.

If it is true then why board uses level shifter?

Hi there,

I was checking over the schematic and the design. I have one small concern about the design surrounding the 1.2v regulator and the 3.3v regulator. You have the 1.2v output driving the 3.3v enable pin. Checking the datasheet for the 3.3v regulator however shows:

Chip enable: Applying VEN < 0.4 V disables the regulator, Pulling VEN > 1.2 V enables the LDO

My concern is that the 1.2v output driving this pin is right on the threshold and if the 1.2v dips it could cause the 3.3v to turn off. I seem to recall the ICE40 datasheet showing that the powerup sequence should have 1.2v starting before 3.3v which is why I guess its wired like this.

Would a simple RC circuit be better in this case driving the enable from the 5v rail?

Hi!

Can you add gerber for those who have no KiCad installed?
I've tried to import it to Altium Designer (which i'm familiar to), but result wasn't good.

There are literally 0 IC of this in the market, in order to build this.
Is this possible that the whole thing works with another FPGA chip that you can find in the market?

Perhaps one from the same product line?