d-m-bailey / cvc Goto Github PK

getnet to show connection counts
getdevice to show connections

The internal net of 2 on nmos with respect to high signal is calculated as min high-Vth.
Then there is a short detected from hi to high-Vth

The internal net of 2 on pmos connected to vss is calculated as max -Vthp.
Then there is a short detected from vss to -Vthp.

Currently, resistor chain calculations are for min/sim/max simultaneously. Allowances to calculate them separately, would offer better coverage. For example, with a VPP - VSS chain with possible VSS cutoff,
allow min voltage to be calculated, but max voltage would be VPP. Sim voltage may be undefined.

Only compare min/min, max/max. Don't do min/max comparison.
Related to comparison to creating voltage.

Currently cvcrc.default
Proposed default.cvcrc

interferes with new makefile

Capacitor connected via one path resistor to intermediate node.
getnet shows paths to power/ground but report file only shows paths to intermeditate node with no voltages.

For example, |VSS| should be ok if expanded to VSS 0.0

Currently only a power signal and its alias are checked against another signal, its alias and relatives.

Common relatives should also indicate a relationship.

Add an intersection function to the unordered_set class.

For each element of the smallest set:
Check for matching element in largest set:
if found, return true
return false

given VDD < VCC
if the output of a VDD inverter is tied to the output of a VCC inverter, no error.

should be an error on the VDD inverter pmos input, but no error is detected if the max gate is not < the min drain gate.

VDD inverter pmos: gate (VSSVDD), source(VDD), drain(VSSVCC)
first check gate-source VDD !< VDD, no error,
second check gate-drain VDD < VCC, but VDD !> min(source)

change to check gate > min(source, drain)

opposite checks for nmos

Doesn't match (CELL)/XAOMETHING_*/XREALCELL/OUT

for subckt's with only power input, only expand one instance for each power combination.

debug command creates a cvcrc file, a cdl netlist, a power file, and a model file for the current instance.

Also change gDebug to const variable to skip debug checks in regular execution.

When rerunning or resetting power file, get memory already released error.

step up/down voltages are calculated with the expectation of a pull up/down path.
in bias error checking of pmos back bias = 0V, we get false errors to calculated voltages that do not have expected pull up/down paths.

Also in tie hi/lo outputs from mosdiode loopback circuits.

High voltage tolerant I/O detects an error across min/max terminals even when calculated from same net.

Voltage calculation from first pass is ignored if no logical pull up/down in second pass.

Hi-V -> VREF-N -> mid -> OFF-NMOS -> ground. max mid is detected as Hi-V.

read model/power files before netlist.

find syntax errors in model/power files before reading netlist.
read model file first to set Vth for mos and possibly diodes.
use model vth in power settings.
requires 2 passes to read model/power files because depend on each other.

returns the most previous logically equivalent net

only available after inverter chains have been calculated

gate-source errors should? be ignored for floating source/drain, maybe.

Ignore case for model parameter column headings for model, condition, diode.

nmos: if min gate is greater than min source/drain sim, compare min source to min drain, max source to max drain.
pmos: if max gate is less than max source/drain sim, compare min source to min drain, max source to max drain.

Flag nets only connected to one device.
Possibly ignore nets connected to devices that are always off.
Customer wants to find floating mos capacitors.

flush the interactive output log before every input prompt

currently progress is displayed on a scrolling screen.
overwrite last progress line instead

list nets that are candidates for power definitions
unbalanced nmos/pmos connections
bulk connections

Move unexpected diode errors to error file. (already processing mos diodes). When printing summaries maybe group by device types.

summarize and limit.

Don't display all unexpected voltages. only those that indicate a problem. (lower min voltages or higher max voltages)
copy the family from power alias

double pmos diode where bottom source max already defined yields no warning for VSS connection.
Should give expected VDD-2Vth found VSS

opposite for nmos

keep counts in right justified columns

1. foreach model : calculate modelname length + count length and save maxFieldSize

2. foreach model: left print modelname, right print count in field size maxFieldSize - modelname length
   nmos..53
pmos_n.2
diode..5

where dots are spaces

Should be no error if same nets.

Currently runtime displayed is from the start of the program.
Reset runtime on each restart.
Do not include interactive time in run time.

if there is a path to only one voltage, ignore the resistance.

Add GPLv3 display on startup.

latch output is dependent on clock input.
however, on reset, output should be fixed regardless on clock input.

check mos connections for same power/same output. opposite power.

Currently assumes descending queue count and processes the queue with most entries first.
If queue count is increasing, that queue will always have priority until it decreases less than the other.

check based on ascending/descending. decreasing: largest queue gets priority increasing: smallest queue get priority

sim propagation through resistors ignores unknown mos gates.
this leads to false off states causing false floating errors.
stop sim resistor propagation when net is connected to non-resistor devices.
save stopped nets and warn when min/max resistor propagation does not have both pull up/down.

Write results to separate files and merge when finished.

R=l/nfin1000000000000 -> R=l/nfin1e12 or R=l/nfin*1T

transfer gates forced on with low input cause unexpected min voltage error.
transfer gates should be exempt from mos diode checks.

No error message in log for resistor chains that aren't calculated.

False error for mos caps connected to mosdiodes.
can't find initial max power ???
checked saved max leak power and power lookup

Parasitic diodes are in the model definitions, but not actually checked.
Replace BIAS error with PARASITIC_DIODE error.

Normally Hi-Z checks are ignored if there is no leak path. However, if the gate net has no connections to any conducting device, an error is detected even if there is no leak path. A "* no leak path" message is generated.

Input nets that have min||max defined but sim value as open, should not flag an error if there is no leak path.

keyword 'ignore' as a model type skips the device.

Split power/model file processing into before/after netlist read.
Before: syntax checks.
After: existence checks.

In power file, allow macros referencing model file parameters.
For example, Vth[NCH] is the Vth defined for NCH.

Model condition processing only uses certain parameters. Don't save netlist parameters unless used in conditions.

initial calculated max is lost. second min/max pass should use sim value for min and max.