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riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

riscv-crypto

RISC-V cryptography extensions standardisation work.

riscv-debian

A set of scripts to build a (somewhat) working Debian image for RISC-V.

riscv-dv

riscv-emu

RISC-V emulator that is written in Rust. Support Linux, xv6, NuttX, FreeRTOS, Zephyr OS etc.

riscv-isa-extension-for-sm4

RISC-V instruction set extensions for SM4 block cipher

riscv-multi-cycle

WIP - A multi-cycle implementation of the RISCV rv32ui architecture.

riscv-opcodes

RISC-V Opcodes

riscv-openocd

Fork of OpenOCD that has RISC-V support

riscv_cpu

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

riscv_gnu_eclipse

Eclipse Plugin for RISC-V GNU Toolchain

riscv_jtag_server

riscv_soc

Basic RISC-V Test SoC

riscv_vhdl

VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".

rsd

RSD: RISC-V Out-of-Order Superscalar Processor

rudi-rv32i

A rudimental RISCV CPU supporting RV32I instructions, in VHDL

rv12

RISC-V CPU Core

rvkrypto-fips

FIPS and higher-level algorithm tests for RISC-V Crypto Extension

scarv-cpu

SCARV: a side-channel hardened RISC-V platform

scastie

An interactive playground for Scala

scintillanet

A Windows Forms control, wrapper, and bindings for the Scintilla text editor.

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

screentogif

🎬 ScreenToGif allows you to record a selected area of your screen, edit and save it as a gif or video.

sdram-controller

Verilog SDRAM memory controller

sds7102

A port of Linux to the OWON SDS7102 scope

serial_link

A simple, scalable, source-synchronous, all-digital DDR link

serv

SERV - The SErial RISC-V CPU

sha256

Hardware implementation of the SHA-256 cryptographic hash function

sha256-animation

Animation of the SHA-256 hash function in your terminal.

shadowsocks_install

Auto Install Shadowsocks Server for CentOS/Debian/Ubuntu