Comments (1)
Fixed by f72e5ec
from filament.
Related Issues (20)
- Inter-pipeline Data Access HOT 1
- Are Guards Needed in Absence of Sharing? HOT 4
- Automatically mark ports as `@stable` in Calyx backend
- `with` construct to clean up pipeline stage definition
- Stream ports HOT 1
- Interpreting interface signals in continuous pipelines
- Ensure all ports of this component are assigned to
- Optional defauts for event variables HOT 1
- Using `@phantom` port in a module should be an error
- Generate efficient FSMs for slow modules HOT 2
- Pretty printer does not print parameters for modules
- Using indicator variable for constraint checking HOT 6
- Checking sharing with `for` loops
- Expressing backend capabilities using parameter bounds
- Linearity check for port assignments HOT 4
- Allow terminating recursion HOT 2
- Bundles in component signatures
- Require parameters usage to be non-negative
- Generate Filament stub from Verilog module
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from filament.