Comments (1)
One thought that came up while talking to @sampsyo is that the @interface
stuff is currently used to reason about two properties: the minimum safe initiation interval for inter-pipeline conflicts, and the minimum amount of time before a resource and be reused for intra-pipeline conflicts. If we could separate the two out, we could say that a Register that uses its prev
port cannot be reused for the rest of the pipeline's execution. This has the benefit of returning the "sane" semantics of prev
ports where they will always contain the value stored in the previous iteration of the pipeline
from filament.
Related Issues (20)
- Are Guards Needed in Absence of Sharing? HOT 4
- Automatically mark ports as `@stable` in Calyx backend
- `with` construct to clean up pipeline stage definition
- Stream ports HOT 1
- Interpreting interface signals in continuous pipelines
- Ensure all ports of this component are assigned to
- Optional defauts for event variables HOT 1
- Allow user-level components to specify `@phantom` ports HOT 1
- Using `@phantom` port in a module should be an error
- Generate efficient FSMs for slow modules HOT 2
- Pretty printer does not print parameters for modules
- Using indicator variable for constraint checking HOT 6
- Checking sharing with `for` loops HOT 3
- Expressing backend capabilities using parameter bounds
- Linearity check for port assignments HOT 4
- Allow terminating recursion HOT 2
- Bundles in component signatures
- Require parameters usage to be non-negative HOT 1
- Generate Filament stub from Verilog module
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from filament.