ctag-fh-kiel / ctag-straempler

An open source eurorack sample streaming and sound synthesis module.

CTAG Strämpler

This repository contains the firmware and the hardwaredesigns (CTAG and Antumbra) of Strämpler.

!!NEW!! Strämpler firmware can now be built in the cloud using Github actions !!NEW!! Strämpler can now run CTAG TBD as alternative firmware! Enclosed in /bin folder!

What it is:

• Half streamer, half sampler, therefore called Strämpler (close to German word of Strampler meaning romper suit).
• Allows streaming of large audio files from SD card (limit 2GB file size due to FAT32 used).
• A eurorack modular synth module with 22 HP width and an internet connection.
• A bridge to connect to freesound.org, to play with samples within your modular synth setup.
• Allows tweaking of your sound just like you'd do with a sampler + a modular synth.
• Allows to parameter tweak and modulate sounds by control voltage (CV), employing a complex modulation matrix.

Why it is:

• A group of audio enthusiasts enjoying coding and hardware making.
• The sexiness of sampling for sound design and synthesis.
• The (subjective) need to have more sampling modules in the eurorack modular synth domain.
• The (subjective) need to make eurorack more compatible with internet of things.
• Build a platform to learn, build and practise skills, and engage students.
• To allow anyone to understand technology by offering open access.
• To benchmark the capabilities of the WiFi/BLE enabled Espressif ESP32 platform and get a deep understanding of it.
• To squeeze and optimize code so that it can work on a small embedded system.
• Because we can.
• Because of some inspiration of the Elektron Octatrack.

Features:

• 2 voice eurorack sample streaming module.
• Streaming of large sound files from SD-card (limited by FAT32 2GB).
• Internet connection to freesound.org, allows to download files through freesound.org api onto SD-card of module.
• One ADSR per voice to control sample amplitude.
• One band pass filter per voice with controllable base, width and Q. Can be used as low / high pass (biquad implmentation).
• Arbitrary playback speed adjustment (+/- 100%).
• Pitching +/- 12 halftones, samples can be played e.g. using external gate / CV keyboard.
• Distortion per voice (tanh() saturation).
• Delay as send effect (stereo, ping pong, max delay time 1.5s).
• External stereo input, with delay send, mix with voices.
• Modulation matrix, where many parameters can be modulated using external CV.
• Gate and latch modes for sample playback.
• REST-API for user file upload (service discovery by MDNS / bonjour).
• 44.1kHz, 32 bit float internal resolution, 24 bit codec resolution, 12 bit CV input resolution sampled at 2KHz (yes, modulation in the audio range is possible to a certain extend), approx. 1ms DSP buffer latency (32 words per channel).
• Approx. 100mA +12V / 10mA -12V power draw.

Potential new features / current limitations / work to be done:

• Sampling of external input.
• Upload to freesound.org.
• Improved sound browser, browse by tag, browse by search.
• More testing of modulation.
• More effects.
• More performance optimization.
• Automatic voice alternation.
• Bug identification and fixing.
• Code refactoring to make things more beautiful.
• More user friendly interaction.
• Documentation / tutorials.
• Your ideas?

How to engage yourself:

• Join the enthusiastic developer team on Github.
• Help build and spread the hardware module (and the word).
• Use Strämpler to create cool sounds and music and share them (with a link to us).
• More ideas?

Words of caution:

• CTAG Strämpler does contain bugs, it comes without warranty of any kind, none of the authors are liable to damages arising by the use of it.
• CTAG Strämpler is an intermediate to advanced project, both in terms of hardware and software design:
  • In order to build the hardware you need intermediate to advanced SMD soldering skills and respective tools. I.e. the PCB contains many 0604 SMD components as well as TSSOP packages and a QFN. However, with a bit of practise you will be able to DIY build your own module. Dare and be rewarded, tackle the frustration on the path, it's worth it. The idea of the platform is also to boost your soldering skills, it CAN all be done by hand.
  • The software is built using Espressif IDF using the C programming language. Intermediate knowledge of C is required to understand the code. Furthermore, some basic DSP algorithms are applied. A DSP newbie, however, could take the project to really get rolling and build up on DSP capabilities. CTAG Strämpler is ideal to try out and play with your own DSP algorithms.
• The Espressif ESP32 platform used for CTAG Strämpler is, with regard to its computational power and I/O capabilities, hard at its limit. We're squeezing the platform here and are already surprised, what one can get out of $5 chip in the year 2019. Surely, other DSPs / microcontrollers could do a better job, but do they allow for internet of things as easily?

How to get started / user manual:

See the Wiki pages of this project.

Build instructions

The easiest way is to create a fork on Github from this repository. Then make sure GitHub Actions are activated for your fork by going to the corresponding tab at your fork and clicking on the green button. Every time you push new commits into your fork (master or dev branch) the action will build a new draft release, which will upon successful run of the action be available at your fork's release tab.

If you want to build on your own system, you can use a virtual development environment image with Docker (see here for ESP IDF Docker instructions). Here are some steps:

• Install Docker
• Install Git
• Open a command line shell
• Clone the Strämpler repository and submodules with git clone --recurse-submodules https://github.com/ctag-fh-kiel/ctag-straempler.git and change into it with cd ctag-straempler
• Build the firmware with docker run --rm -v $PWD:/project -w /project rma31/idf:v4.1-strampler idf.py build

You can edit the source files using any IDE / text editor you like.

Flash instructions

• Either download the firmware from the Github release tab or use your own
• Install ESP Tool
• Adapt the Firmware flash script to your system needs and flash the firmware

Hardware

All hardware design can be found https://github.com/ctag-fh-kiel/esp32-eurorack-audio.

Links

• Demonstration videos on YouTube.

Licenses:

• Hardware is licensed under Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0).
• Software licenses, see license file.
• Freesound license: Freesound.org API terms and here as well as the freesound website terms of use.
• Don't forget to obey the license of the respective sound files used in your music. License details are shown for the individual sound file in your CTAG Strämpler sound browser, including the sound file authors name.

Who made this happen:

• The team of CTAG (Creative Technologies Arbeitsgruppe) at Kiel University of Applied Science, including:
  • Robert Manzke
  • Phillip Lamp
  • Niklas Wantrupp
  • With kind support for the front panel design by David Knop from instruments of things.
• Antumbra
• More people like you :)

ctag-straempler's Issues

firmware crashes when trying to edit effects or cv matrix.

firmware crashes when trying to edit effects or cv matrix. pretty much says it all. Firmware is the ready built version in the bin folder. When crashed the screen will freeze and all functionality stops.

Cannot access freesounds.org

I have built and flashed the unit OK, it goes online, (the time updates) but when i go to slots/slot 1/freesounds.org nothing happens. I have checked the setup file and the api key matches my key on freesounds. not sure what to try now?

cv6 and cv7 don't work in the CV Matrix

I was in the process of testing that all my CV input were working correctly.

So I tried mapping the various CV input to a property e.g. V0 Volume. (I also tried a few others)

CV3 4 altered the volume from medium loudness to full loudness (is this correct?)
CV5 and CV8 varied the volume correctly from silence to full volume
CV6 and CV 7 made to difference at all to volume

I checked the voltages on the input pins to the ADC and they all varied from 0v->3.3V

So, I assume it's a software issue?

I checked the logs but nothing seems to be logged around those operations
Thanks

esp-adf

Hello. why don't you use ESP-ADF?

Separate voice outputs

It would be nice if the output could be configured to be either stereo or mono for both slots. Same for the inputs!

Setting up toolchain as per instructions - failed ! (My fault but struggling)

I’m really struggling to build the firmware.
I’ve followed the instructions to the letter
I have unpacked the binary download of gcc 8.2

I am really unsure whether and how to replace the xtensa / esp-idf toolchain
I’ve tried changing my path to the gcc 8.2 and setting the prefix in the menuconfig
But I’m really struggling to setup the paths to gcc 8.2
I cant find anything useful on the esp forums.

I appreciate it’s not really an issue with the code but dont know how else to ask for help !

SD Card

In order for the ESP32 to read/write to the SD card, I had to make a 4Gb partition on my 16Gb card. It then writes the config files to the card.

Sample start, loop start/stop positions need update when sound changed

Sample start, loop start/stop positions seem to remain calculated for the previous sample, if new sample is loaded. They are set correctly once one edits the value in the playmodes menu.
Needs fix that values are set correctly upon new sound to slot assignment.

Wifi boot

Issue when available extra power is low and WIFI is not recognised: the module keeps restarting. Entering the wifi data via editing the config file on the SD card solved the issue. Possible solution would be disabling wifi on boot by pressing some combination of buttons, and re-enabling it when a new wifi password is entered. It would be nice if the module could store more wifi passwords at once.

diskio_sdmmc: sdmmc_read_blocks failed

Hi.

I have only tried with one SD card but this looks like there is a problem with it I guess. When I use the flash.sh file, the files are written to the card and the SD examples work fine. This is the serial monitor output :

rst:0x1 (POWERON_RESET),boot:0x1b (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:4
load:0x3fff0034,len:7316
load:0x40078000,len:14252
load:0x40080400,len:4688
entry 0x400806a4
�[0;32mI (28) boot: ESP-IDF v4.1.2-95-gaeb66e1057 2nd stage bootloader�[0m
�[0;32mI (28) boot: compile time 09:31:00�[0m
�[0;32mI (28) boot: chip revision: 1�[0m
�[0;32mI (32) boot_comm: chip revision: 1, min. bootloader chip revision: 0�[0m
�[0;32mI (39) qio_mode: Enabling default flash chip QIO�[0m
�[0;32mI (44) boot.esp32: SPI Speed : 40MHz�[0m
�[0;32mI (49) boot.esp32: SPI Mode : QIO�[0m
�[0;32mI (53) boot.esp32: SPI Flash Size : 4MB�[0m
�[0;32mI (58) boot: Enabling RNG early entropy source...�[0m
�[0;32mI (63) boot: Partition Table:�[0m
�[0;32mI (67) boot: ## Label Usage Type ST Offset Length�[0m
�[0;32mI (74) boot: 0 nvs WiFi data 01 02 00009000 00006000�[0m
�[0;32mI (82) boot: 1 phy_init RF data 01 01 0000f000 00001000�[0m
�[0;32mI (89) boot: 2 factory factory app 00 00 00010000 00200000�[0m
�[0;32mI (97) boot: End of partition table�[0m
�[0;32mI (101) boot_comm: chip revision: 1, min. application chip revision: 0�[0m
�[0;32mI (108) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f400020 size=0x2f0f0 (192752) map�[0m
�[0;32mI (187) esp_image: segment 1: paddr=0x0003f118 vaddr=0x3ffb0000 size=0x00f00 ( 3840) load�[0m
�[0;32mI (189) esp_image: segment 2: paddr=0x00040020 vaddr=0x400d0020 size=0xc7854 (817236) map�[0m
�[0;32mI (491) esp_image: segment 3: paddr=0x0010787c vaddr=0x3ffb0f00 size=0x05628 ( 22056) load�[0m
�[0;32mI (501) esp_image: segment 4: paddr=0x0010ceac vaddr=0x40080000 size=0x00404 ( 1028) load�[0m
�[0;32mI (501) esp_image: segment 5: paddr=0x0010d2b8 vaddr=0x40080404 size=0x1e134 (123188) load�[0m
�[0;32mI (579) boot: Loaded app from partition at offset 0x10000�[0m
�[0;32mI (579) boot: Disabling RNG early entropy source...�[0m
�[0;32mI (580) psram: This chip is ESP32-D0WD�[0m
�[0;32mI (584) spiram: Found 64MBit SPI RAM device�[0m
�[0;32mI (589) spiram: SPI RAM mode: flash 80m sram 80m�[0m
�[0;32mI (594) spiram: PSRAM initialized, cache is in low/high (2-core) mode.�[0m
�[0;32mI (601) cpu_start: Pro cpu up.�[0m
�[0;32mI (605) cpu_start: Application information:�[0m
�[0;32mI (610) cpu_start: Project name: ctag-straempler�[0m
�[0;32mI (616) cpu_start: App version: v0.9�[0m
�[0;32mI (620) cpu_start: Compile time: Sep 11 2021 09:54:10�[0m
�[0;32mI (626) cpu_start: ELF file SHA256: 32bab0cc5eb6c006...�[0m
�[0;32mI (632) cpu_start: ESP-IDF: v4.1.2-95-gaeb66e1057�[0m
�[0;32mI (638) cpu_start: Starting app cpu, entry point is 0x40081720�[0m
�[0;32mI (0) cpu_start: App cpu up.�[0m
�[0;32mI (1121) spiram: SPI SRAM memory test OK�[0m
�[0;32mI (1121) heap_init: Initializing. RAM available for dynamic allocation:�[0m
�[0;32mI (1121) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM�[0m
�[0;32mI (1128) heap_init: At 3FFBEEB0 len 00021150 (132 KiB): DRAM�[0m
�[0;32mI (1134) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM�[0m
�[0;32mI (1140) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM�[0m
�[0;32mI (1147) heap_init: At 4009E538 len 00001AC8 (6 KiB): IRAM�[0m
�[0;32mI (1153) cpu_start: Pro cpu start user code�[0m
�[0;32mI (1158) spiram: Adding pool of 4096K of external SPI memory to heap allocator�[0m
�[0;32mI (1178) spi_flash: detected chip: generic�[0m
�[0;32mI (1178) spi_flash: flash io: qio�[0m
�[0;32mI (1178) cpu_start: Starting scheduler on PRO CPU.�[0m
�[0;32mI (0) cpu_start: Starting scheduler on APP CPU.�[0m
�[0;32mI (1188) SD: Initializing SD card�[0m
�[0;32mI (1188) gpio: GPIO[13]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0 �[0m
Name: SD64G
Type: SDHC/SDXC
Speed: 40 MHz
Size: 59640MB
SPI: display device added to spi bus (1)

SPI: attached display device, speed=8000000

SPI: bus uses native pins: false

SPI: display init...

OK

SPI: Max rd speed = 1000000

SPI: Changed speed to 26666666

�[0;32mI (2688) gpio: GPIO[33]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:2 �[0m
�[0;32mI (2688) gpio: GPIO[34]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:2 �[0m
�[0;32mI (2698) gpio: GPIO[35]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:2 �[0m
�[0;32mI (2708) gpio: GPIO[36]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0 �[0m
�[0;32mI (2718) gpio: GPIO[39]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0 �[0m
�[0;32mI (2728) AUDIO: Starting audio task�[0m
�[0;32mI (2728) I2S: DMA Malloc info, datalen=blocksize=256, dma_buf_count=4�[0m
�[0;32mI (2738) I2S: DMA Malloc info, datalen=blocksize=256, dma_buf_count=4�[0m
�[0;32mI (2758) I2S: APLL: Req RATE: 44100, real rate: 44099.988, BITS: 32, CLKM: 1, BCK_M: 8, MCLK: 22579194.000, SCLK: 2822399.250000, diva: 1, divb: 0�[0m
�[0;31mE (2798) sdmmc_cmd: sdmmc_read_sectors_dma: sdmmc_send_cmd returned 0x109�[0m
�[0;31mE (2798) diskio_sdmmc: sdmmc_read_blocks failed (265)�[0m
�[0;31mE (2798) FILEIO: Error reading from file�[0m
�[0;31mE (2798) PRESET: Root is NULL�[0m
�[0;31mE (2808) MENU: Error loading bank from file�[0m
�[0;31mE (2808) MENU: Error loading bank�[0m
�[0;31mE (2818) sdmmc_cmd: sdmmc_read_sectors_dma: sdmmc_send_cmd returned 0x107�[0m
�[0;31mE (2818) diskio_sdmmc: sdmmc_read_blocks failed (263)�[0m
�[0;31mE (2828) FILEIO: Could not allocate memory�[0m
�[0;31mE (2828) MENU: Error loading tz_shift from config�[0m
I (2988) wifi:wifi driver task: 3ffe9e1c, prio:23, stack:6656, core=0
�[0;32mI (2988) system_api: Base MAC address is not set, read default base MAC address from BLK0 of EFUSE�[0m
�[0;32mI (2988) system_api: Base MAC address is not set, read default base MAC address from BLK0 of EFUSE�[0m
I (3008) wifi:wifi firmware version: 1424aca
I (3008) wifi:config NVS flash: enabled
I (3008) wifi:config nano formating: disabled
I (3008) wifi:Init data frame dynamic rx buffer num: 32
I (3018) wifi:Init management frame dynamic rx buffer num: 32
I (3018) wifi:Init management short buffer num: 32
I (3028) wifi:Init static tx buffer num: 16
I (3028) wifi:Init static rx buffer size: 1600
I (3038) wifi:Init static rx buffer num: 10
I (3038) wifi:Init dynamic rx buffer num: 32
�[0;32mI (3048) wifi_init: rx ba win: 16�[0m
�[0;32mI (3048) wifi_init: tcpip mbox: 32�[0m
�[0;32mI (3048) wifi_init: udp mbox: 6�[0m
�[0;32mI (3058) wifi_init: tcp mbox: 6�[0m
�[0;32mI (3058) wifi_init: tcp tx win: 5744�[0m
�[0;32mI (3068) wifi_init: tcp rx win: 5744�[0m
�[0;32mI (3068) wifi_init: tcp mss: 1440�[0m
�[0;32mI (3068) wifi_init: WiFi/LWIP prefer SPIRAM�[0m
�[0;32mI (3078) wifi_init: WiFi IRAM OP enabled�[0m
�[0;32mI (3078) wifi_init: WiFi RX IRAM OP enabled�[0m
�[0;31mE (3088) sdmmc_req: handle_idle_state_events unhandled: 00000008 00000002�[0m
�[0;32mI (3098) WIFI: Setting WiFi configuration SSID Fantasy Man�[0m
�[0;32mI (3098) phy_init: phy_version 4660,0162888,Dec 23 2020�[0m
�[0;33mW (3108) phy_init: failed to load RF calibration data (0x1102), falling back to full calibration�[0m
ets Jun 8 2016 00:22:57

rst:0x1 (POWERON_RESET),boot:0x1b (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0⸮⸮半⸮⸮⸮_drv:0x00,q_drv:0x00,d_drv:0x00,c⸮ߤ⸮⸮⸮⸮⸮⸮⸮⸮hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:4
load:0x3fff0034,len:7316
load:0x40078000,len:14252
load:0x40080400,len:4688
entry 0x400806a4
�[0;32mI (28) boot: ESP-IDF v4.1.2-95-gaeb66e1057 2nd stage bootloader�[0m
�[0;32mI (28) boot: compile time 09:31:00�[0m
�[0;32mI (28) boot: chip revision: 1�[0m
�[0;32mI (32) boot_comm: chip revision: 1, min. bootloader chip revision: 0�[0m
�[0;32mI (39) qio_mode: Enabling default flash chip QIO�[0m
�[0;32mI (44) boot.esp32: SPI Speed : 40MHz�[0m
�[0;32mI (49) boot.esp32: SPI Mode : QIO�[0m
�[0;32mI (53) boot.esp32: SPI Flash Size : 4MB�[0m
�[0;32mI (58) boot: Enabling RNG early entropy source...�[0m
�[0;32mI (63) boot: Partition Table:�[0m
�[0;32mI (67) boot: ## Label Usage Type ST Offset Length�[0m
�[0;32mI (74) boot: 0 nvs WiFi data 01 02 00009000 00006000�[0m
�[0;32mI (82) boot: 1 phy_init RF data 01 01 0000f000 00001000�[0m
�[0;32mI (89) boot: 2 factory factory app 00 00 00010000 00200000�[0m
�[0;32mI (97) boot: End of partition table�[0m
�[0;32mI (101) boot_comm: chip revision: 1, min. application chip revision: 0�[0m
�[0;32mI (108) esp_image: segment 0: paddr=0x00010020 vaddr=0x3f400020 size=0x2f0f0 (192752) map�[0m
�[0;32mI (187) esp_image: segment 1: paddr=0x0003f118 vaddr=0x3ffb0000 size=0x00f00 ( 3840) load�[0m
�[0;32mI (189) esp_image: segment 2: paddr=0x00040020 vaddr=0x400d0020 size=0xc7854 (817236) map�[0m
�[0;32mI (491) esp_image: segment 3: paddr=0x0010787c vaddr=0x3ffb0f00 size=0x05628 ( 22056) load�[0m
�[0;32mI (501) esp_image: segment 4: paddr=0x0010ceac vaddr=0x40080000 size=0x00404 ( 1028) load�[0m
�[0;32mI (501) esp_image: segment 5: paddr=0x0010d2b8 vaddr=0x40080404 size=0x1e134 (123188) load�[0m
�[0;32mI (579) boot: Loaded app from partition at offset 0x10000�[0m
�[0;32mI (579) boot: Disabling RNG early entropy source...�[0m
�[0;32mI (580) psram: This chip is ESP32-D0WD�[0m
�[0;32mI (584) spiram: Found 64MBit SPI RAM device�[0m
�[0;32mI (589) spiram: SPI RAM mode: flash 80m sram 80m�[0m
�[0;32mI (594) spiram: PSRAM initialized, cache is in low/high (2-core) mode.�[0m
�[0;32mI (601) cpu_start: Pro cpu up.�[0m
�[0;32mI (605) cpu_start: Application information:�[0m
�[0;32mI (610) cpu_start: Project name: ctag-straempler�[0m
�[0;32mI (616) cpu_start: App version: v0.9�[0m
�[0;32mI (620) cpu_start: Compile time: Sep 11 2021 09:54:10�[0m
�[0;32mI (626) cpu_start: ELF file SHA256: 32bab0cc5eb6c006...�[0m
�[0;32mI (632) cpu_start: ESP-IDF: v4.1.2-95-gaeb66e1057�[0m
�[0;32mI (638) cpu_start: Starting app cpu, entry point is 0x40081720�[0m
�[0;32mI (0) cpu_start: App cpu up.�[0m
�[0;32mI (1121) spiram: SPI SRAM memory test OK�[0m
�[0;32mI (1121) heap_init: Initializing. RAM available for dynamic allocation:�[0m
�[0;32mI (1121) heap_init: At 3FFAE6E0 len 00001920 (6 KiB): DRAM�[0m
�[0;32mI (1128) heap_init: At 3FFBEEB0 len 00021150 (132 KiB): DRAM�[0m
�[0;32mI (1134) heap_init: At 3FFE0440 len 00003AE0 (14 KiB): D/IRAM�[0m
�[0;32mI (1140) heap_init: At 3FFE4350 len 0001BCB0 (111 KiB): D/IRAM�[0m
�[0;32mI (1147) heap_init: At 4009E538 len 00001AC8 (6 KiB): IRAM�[0m
�[0;32mI (1153) cpu_start: Pro cpu start user code�[0m
�[0;32mI (1158) spiram: Adding pool of 4096K of external SPI memory to heap allocator�[0m
�[0;32mI (1178) spi_flash: detected chip: generic�[0m
�[0;32mI (1178) spi_flash: flash io: qio�[0m
�[0;32mI (1178) cpu_start: Starting scheduler on PRO CPU.�[0m
�[0;32mI (0) cpu_start: Starting scheduler on APP CPU.�[0m
�[0;32mI (1188) SD: Initializing SD card�[0m
�[0;32mI (1188) gpio: GPIO[13]| InputEn: 0| OutputEn: 1| OpenDrain: 0| Pullup: 0| Pulldown: 0| Intr:0 �[0m
Name: SD64G
Type: SDHC/SDXC
Speed: 40 MHz
Size: 59640MB
SPI: display device added to spi bus (1)

SPI: attached display device, speed=8000000

SPI: bus uses native pins: false

SPI: display init...

I guess I should try another SD card ?

Thanks :)

Encoder direction

Is there a way to reverse the encoder direction?
Thanks

Crash when sound file assigned but raw file not existing

Sound file assignment needs better checks. Can be fixed manually by deleting data on sd-card (corrupt sound files and config.jsn for assignment).

Display just stays white...

Hi, have an issue to get the display to work its a slightly different one from ali express with jumper on the back. So probably there is a =nother driver and that's why it doesn't work or something with the connection i guess...order a new display and will try that first...if its SPI connection what's the prob, how can i test?

Thanks and awesome keep up the good work...also some small advice: maybe write a bit more about the software part. PIN 6 to Ground to flash and such like that would be helpful:)

Playback partially corrupted when start + PBspeed modulated

Seems as if playback goes beyond sample limit, resulting in noise and partially crashes...
Seems to happen only in single shot mode.

Crashes and reboots when trying to download FreeSound sound by ID

Repro steps:

1. Select Sample
2. Select ID
3. Enter a valid FreeSound ID e.g. 123

Unit crashes and reboots (My token replaced with xxxxxx)
A few observations:

• the port appears incorrect, as it should be 443
• Assuming this URL is to retrieve metadata should it include the 'format' parameter eg. 'https://freesound.org/apiv2/sounds/123/?format=json&token=xxxxxx'

Logs:

W (92316) id: 123
I (93116) HTTP_REQ: Following: https://freesound.org:80/apiv2/sounds/123/?token=xxxxxx
Guru Meditation Error: Core 0 panic'ed (LoadProhibited). Exception was unhandled.
Core 0 register dump:
PC : 0x4018e9b7 PS : 0x00060a30 A0 : 0x80175d84 A1 : 0x3ffecbe0
A2 : 0x00000000 A3 : 0xffffffff A4 : 0x00000001 A5 : 0x3ffecab0
A6 : 0x00000087 A7 : 0x3ffecab0 A8 : 0x3ffae940 A9 : 0x00000087
A10 : 0x00000000 A11 : 0x3ffecaf4 A12 : 0x3ffecad4 A13 : 0x00000000
A14 : 0x0000005c A15 : 0xff000000 SAR : 0x00000004 EXCCAUSE: 0x0000001c
EXCVADDR: 0x00000018 LBEG : 0x4008b535 LEND : 0x4008b545 LCOUNT : 0xffffffe8

ELF file SHA256: 4a55c6babb07d1bd75da8f939e30e0b3cd5f2871fb7e3cee016c99f74212d90c

Backtrace: 0x4018e9b7:0x3ffecbe0 0x40175d81:0x3ffecc00 0x4016b286:0x3ffecc20 0x4016bff6:0x3ffecc40 0x40127066:0x3ffecd00

Rebooting...

The module is rebooting

When accessing almost any menu item, the module is loaded. Upon entering the SLOT menu, the module will immediately reboot. The presence of an SD card in the slot does not affect this in any way. I think that the problem is in the firmware, maybe I did something wrong. I tried to remove all microcircuits to eliminate their influence, but it did not help. WiFi my phone does not detect from the module, I can not change the wifi settings either. Flashed via USB port, Windows 10. Software -ESP32 Download-Tool v3.6.4

Never ending reboot loop

Hello again,
I am using the firmware in the bin folder
So I got it up and running and it was working fine.
Then I went to settings, entered my wifi credentials and freesound token.
Then I went to slot, and tried to enter a freesound id.
That's when the reboot cycle started.

In the reboot, it displays the splash screen if the SD card is inserted,
and is responsive for about a second. I can see the clock top right gets to about 10:00:05 (my timezone is +10), the screen then freezes, there is a flicker and it restarts

So I removed, the SD and checked the details in it. there are correct.
I tried repowering it with and without SD, it keeps rebooting.
So I finally tried to reflash it, powered it up without SD, and it keeps rebooting.
Then I tried a full flash erase, reflashed, same issue
I then tried the older firmware same behaviour.
I then tried the TBD firmware and that didn't appear to work.
And then I tried to reapply the latest normal firmware, it's back to rebooting

Not sure quite what to do now.
Any help is appreciated.

---

*** This is the info when I reflash:
M:_uBoms_\Strampler\ctag-straempler-master\bin>esptool.py --chip esp32 --port COM9 --before default_reset --after hard_reset write_flash -z --flash_mode dio --flash_freq 80m --flash_size detect 0x1000 bootloader.bin 0x10000 smplr.bin 0x8000 partitions.bin
esptool.py v3.1-dev
Serial port COM9
Connecting........_
Chip is ESP32-D0WD (revision 1)
Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None
Crystal is 40MHz
MAC: ac:67:b2:5b:ae:a4
Uploading stub...
Running stub...
Stub running...
Configuring flash size...
Auto-detected Flash size: 4MB
Flash will be erased from 0x00001000 to 0x00006fff...
Flash will be erased from 0x00010000 to 0x00115fff...
Flash will be erased from 0x00008000 to 0x00008fff...
Flash params set to 0x022f
Compressed 24064 bytes to 14974...
Wrote 24064 bytes (14974 compressed) at 0x00001000 in 1.6 seconds (effective 119.0 kbit/s)...
Hash of data verified.
Compressed 1072208 bytes to 676792...
Wrote 1072208 bytes (676792 compressed) at 0x00010000 in 74.3 seconds (effective 115.4 kbit/s)...
Hash of data verified.
Compressed 3072 bytes to 104...
Wrote 3072 bytes (104 compressed) at 0x00008000 in 0.1 seconds (effective 169.4 kbit/s)...
Hash of data verified.

Leaving...
Hard resetting via RTS pin...

*** Here here are the Fuses:

M:_uBoms_\Strampler\ctag-straempler-master\bin>espefuse.py --port COM9 summary
Connecting........_
Detecting chip type... ESP32
espefuse.py v3.1-dev
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)

Calibration fuses:
BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0)
ADC_VREF (BLOCK0): Voltage reference calibration = 1149 R/W (0b00111)

Config fuses:
XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = False R/W (0b0)
XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = False R/W (0b0)
XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0)
CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 54 R/W (0x36)
SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0b00000)
SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0b00000)
SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0b00000)
SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 0 R/W (0b00000)
SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0b00000)
DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0)

Efuse fuses:
WR_DIS (BLOCK0): Efuse write disable mask = 0 R/W (0x0000)
RD_DIS (BLOCK0): Efuse read disable mask = 0 R/W (0x0)
CODING_SCHEME (BLOCK0): Efuse variable block length scheme
= NONE (BLK1-3 len=256 bits) R/W (0b00)
KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0)

Identity fuses:
MAC (BLOCK0): Factory MAC Address
= ac:67:b2:5b:ae:a4 (CRC 0xb1 OK) R/W
MAC_CRC (BLOCK0): CRC8 for factory MAC address = 177 R/W (0xb1)
CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1)
CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = False R/W (0b0)
CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10)
CHIP_PACKAGE (BLOCK0): Chip package identifier = 1 R/W (0b001)
MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00)

Security fuses:
FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 0 R/W (0b0000000)
UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0)
FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 0 R/W (0x0)
CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1)
ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0)
ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0)
JTAG_DISABLE (BLOCK0): Disable JTAG = False R/W (0b0)
DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0)
DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = False R/W (0b0)
DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = False R/W (0b0)
BLOCK1 (BLOCK1): Flash encryption key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK2 (BLOCK2): Secure boot key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK3 (BLOCK3): Variable Block 3
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W

Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V).

Antumbra hardware has misalligned LCD hole position on the panel PCB

The Antumbra version of hardware has wrong size and placing of the LCD hole on the front panel which covers part of the GUI on the screen. Photo attached.

Unable to flash

Hi there,
I am having an issue trying to flash my strampler.
From what I have read online, it would appear to be a hardware issue. Do you think this could be the case from the logs?
Thanks

This is the chip I am using, which seems to have the Flash onboard: https://au.mouser.com/ProductDetail/356-ESP32-WROVER-IB

This is what the esptool.py output looks like, followed by a fuse summary:

PS M:_uBoms_\Strampler\ctag-straempler-master\bin> esptool.py --chip esp32 --port COM9 --before default_reset --after hard_reset write_flash -z --flash_mode dio --flash_freq 80m --flash_size detect 0x1000 bootloader.bin 0x10000 smplr.bin 0x8000 partitions.bin
esptool.py v3.1-dev
Serial port COM9
Connecting....
Chip is ESP32-D0WD (revision 1)
Features: WiFi, BT, Dual Core, 240MHz, VRef calibration in efuse, Coding Scheme None
Crystal is 40MHz
MAC: ac:67:b2:5b:ae:a4
Uploading stub...
Running stub...
Stub running...
Configuring flash size...
Warning: Could not auto-detect Flash size (FlashID=0x0, SizeID=0x0), defaulting to 4MB
Flash will be erased from 0x00001000 to 0x00006fff...
Flash will be erased from 0x00010000 to 0x00115fff...
Flash will be erased from 0x00008000 to 0x00008fff...
Flash params set to 0x022f
Compressed 24064 bytes to 14974...
Writing at 0x00001000... (100 %)
A fatal error occurred: Timed out waiting for packet header

PS M:_uBoms_\Strampler\ctag-straempler-master\bin> espefuse.py --port COM9 summary
Connecting....
Detecting chip type... ESP32
espefuse.py v3.1-dev
EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value)

Calibration fuses:
BLK3_PART_RESERVE (BLOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0)
ADC_VREF (BLOCK0): Voltage reference calibration = 1149 R/W (0b00111)

Config fuses:
XPD_SDIO_FORCE (BLOCK0): Ignore MTDI pin (GPIO12) for VDD_SDIO on reset = False R/W (0b0)
XPD_SDIO_REG (BLOCK0): If XPD_SDIO_FORCE, enable VDD_SDIO reg on reset = False R/W (0b0)
XPD_SDIO_TIEH (BLOCK0): If XPD_SDIO_FORCE & XPD_SDIO_REG = 1.8V R/W (0b0)
CLK8M_FREQ (BLOCK0): 8MHz clock freq override = 54 R/W (0x36)
SPI_PAD_CONFIG_CLK (BLOCK0): Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0b00000)
SPI_PAD_CONFIG_Q (BLOCK0): Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0b00000)
SPI_PAD_CONFIG_D (BLOCK0): Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0b00000)
SPI_PAD_CONFIG_HD (BLOCK0): Override SD_DATA_2 pad (GPIO9/SPIHD) = 0 R/W (0b00000)
SPI_PAD_CONFIG_CS0 (BLOCK0): Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0b00000)
DISABLE_SDIO_HOST (BLOCK0): Disable SDIO host = False R/W (0b0)

Efuse fuses:
WR_DIS (BLOCK0): Efuse write disable mask = 0 R/W (0x0000)
RD_DIS (BLOCK0): Efuse read disable mask = 0 R/W (0x0)
CODING_SCHEME (BLOCK0): Efuse variable block length scheme
= NONE (BLK1-3 len=256 bits) R/W (0b00)
KEY_STATUS (BLOCK0): Usage of efuse block 3 (reserved) = False R/W (0b0)

Identity fuses:
MAC (BLOCK0): Factory MAC Address
= ac:67:b2:5b:ae:a4 (CRC 0xb1 OK) R/W
MAC_CRC (BLOCK0): CRC8 for factory MAC address = 177 R/W (0xb1)
CHIP_VER_REV1 (BLOCK0): Silicon Revision 1 = True R/W (0b1)
CHIP_VER_REV2 (BLOCK0): Silicon Revision 2 = False R/W (0b0)
CHIP_VERSION (BLOCK0): Reserved for future chip versions = 2 R/W (0b10)
CHIP_PACKAGE (BLOCK0): Chip package identifier = 1 R/W (0b001)
MAC_VERSION (BLOCK3): Version of the MAC field = 0 R/W (0x00)

Security fuses:
FLASH_CRYPT_CNT (BLOCK0): Flash encryption mode counter = 0 R/W (0b0000000)
UART_DOWNLOAD_DIS (BLOCK0): Disable UART download mode (ESP32 rev3 only) = False R/W (0b0)
FLASH_CRYPT_CONFIG (BLOCK0): Flash encryption config (key tweak bits) = 0 R/W (0x0)
CONSOLE_DEBUG_DISABLE (BLOCK0): Disable ROM BASIC interpreter fallback = True R/W (0b1)
ABS_DONE_0 (BLOCK0): Secure boot V1 is enabled for bootloader image = False R/W (0b0)
ABS_DONE_1 (BLOCK0): Secure boot V2 is enabled for bootloader image = False R/W (0b0)
JTAG_DISABLE (BLOCK0): Disable JTAG = False R/W (0b0)
DISABLE_DL_ENCRYPT (BLOCK0): Disable flash encryption in UART bootloader = False R/W (0b0)
DISABLE_DL_DECRYPT (BLOCK0): Disable flash decryption in UART bootloader = False R/W (0b0)
DISABLE_DL_CACHE (BLOCK0): Disable flash cache in UART bootloader = False R/W (0b0)
BLOCK1 (BLOCK1): Flash encryption key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK2 (BLOCK2): Secure boot key
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
BLOCK3 (BLOCK3): Variable Block 3
= 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W

Flash voltage (VDD_SDIO) determined by GPIO12 on reset (High for 1.8V, Low/NC for 3.3V).

accessing via URL

I am having issues using http://ctag-modular/ to access to transfer sounds. I have tried a few different browsers. The module is in the right mode (as per the youtube video) but when I enter the URL i get a "server not found" on the browser.

Unable to build

Hi all! I'm currently working on a ESP32 based synth project and looking for inspiration as this is quite foreign territory for me. While I'm comfortable with ESP-IDF, I feel like something might be missing.

I've ensure I have the latest xtensa tools, IDF is up to date (including submodules, python) but am met with this compilation error.

/home/morgan/devel/ctag-straempler/components/audio/audio.c:76:32: error: missing braces around initializer [-Werror=missing-braces]
 atomic_bool trigModeLatch[2] = {false, false};
                                ^
/home/morgan/devel/ctag-straempler/components/audio/audio.c:76:32: note: (near initialization for 'trigModeLatch')
/home/morgan/devel/ctag-straempler/components/audio/audio.c: In function 'enableTrigModeLatch':
/home/morgan/devel/ctag-straempler/components/audio/audio.c:945:24: error: incompatible types when assigning to type 'atomic_bool {aka struct <anonymous>}' from type 'int'
     trigModeLatch[vid] = true;
                        ^
/home/morgan/devel/ctag-straempler/components/audio/audio.c: In function 'disableTrigModeLatch':
/home/morgan/devel/ctag-straempler/components/audio/audio.c:949:24: error: incompatible types when assigning to type 'atomic_bool {aka struct <anonymous>}' from type 'int'
     trigModeLatch[vid] = false;
                        ^
/home/morgan/devel/ctag-straempler/components/audio/audio.c: In function 'audio_task':
/home/morgan/devel/ctag-straempler/components/audio/audio.c:1033:20: error: used struct type value where scalar is required
                 if(trigModeLatch[vid]){
                    ^
/home/morgan/devel/ctag-straempler/components/audio/audio.c: In function 'assignAudioFiles':
/home/morgan/devel/ctag-straempler/components/audio/audio.c:1179:43: error: 'FIL {aka struct <anonymous>}' has no member named 'cltbl'
                         audio_files[i].fil.cltbl = audio_files[i].clmt;
                                           ^
/home/morgan/devel/ctag-straempler/components/audio/audio.c:1180:43: error: 'FIL {aka struct <anonymous>}' has no member named 'cltbl'
                         audio_files[i].fil.cltbl[0] = SZ_TBL;
                                           ^
/home/morgan/devel/ctag-straempler/components/audio/audio.c: At top level:
cc1: warning: unrecognized command line option '-Wno-int-in-bool-context'
cc1: warning: unrecognized command line option '-Wno-memset-elt-size'
cc1: warning: unrecognized command line option '-Wno-format-truncation'
cc1: warning: unrecognized command line option '-Wno-switch-unreachable'
cc1: warning: unrecognized command line option '-Wno-unused-const-variable'
cc1: warning: unrecognized command line option '-Wno-implicit-fallthrough'
cc1: warning: unrecognized command line option '-Wno-cast-function-type'
cc1: warning: unrecognized command line option '-Wno-misleading-indentation'
cc1: warning: unrecognized command line option '-Wno-stringop-truncation'
cc1: warning: unrecognized command line option '-Wno-format-overflow'
cc1: warning: unrecognized command line option '-Wno-frame-address'

Trying to hack through these just leads to more and one warning of note...

/home/morgan/devel/ESP32/esp-idf/components/esp32/include/rom/lldesc.h:1:2: warning: #warning rom/lldesc.h is deprecated, please use esp32/rom/lldesc.h instead [-Wcpp]

This makes me think you're possibly using an old checkout of IDF?

Where to buy it ?

everylink on modulargrid is dead, the project is open source, but are there any builds available or kits ?