constarg / mips-increase-efficiency-using-pipeline

Simple example for MIPS program's efficiency using the pipeline technology.

Introduction

This repo was created for an exercise for the university.

Details of exercise

This repo consists of 3 codes. The first code is small but not very efficient for the processor. The second code is the same but with a description about the CPI ( Clock Per Instruction ) and other calculations that are relative to the program's efficiency. The third code is a reformat of the first code to help MIPS execute the same instructions but more efficiently using pipeline technology. This repo contains and the C code of the Assembly, for a better understanding of the code. Also in this example, we don't care about how we can improve the code quality ( by making it smarter or removing lines etc ) we only care about how to make this exact code more efficient using the pipeline technology.

pipeline

In both cases of the first and third programs's the simulation is using the pipeline technology as default. However, in the case of the third program, we wrote our code in such a way that we are allowing the processor ( based on the architecture of MIPS with implemented the pipeline technology ) to execute the set of the instructions in our code more efficiently. Execute the instructions more efficiently using pipeline means that the processor, MIPS in our case, is using all its stages ( fetch instruction, decode, execute ) in such a way that we have no delays that are caused by hazards or any other causes that makes a stage unavailable in a clock circle of CPU.

Simulator

• WinMips64

mips-increase-efficiency-using-pipeline's Issues

Too many memory accesses.

As the professor said and is true we access to many times the memory. Make better use of this using the registers of the CPU as temporary space instead.