cidarlab / mint

Mint

Mint is a language to describe Microfluidic Hardware Netlists. Mint is the name of the Microfluidic Netlist language used to describe microfluidic devices for Fluigi to place and route. Mint is a flavor of (MHDL) Microfluidic Hardware Description Language that can be used to represent Microfluidic Circuits.

mint's Issues

Y mixer primitive

It would be helpful to have a y mixer/documentation for a y mixer.

Add Support for comments

Add support for comments both single line and multiline (if possible)

Add support for more layers

Extend the netlist format to support more than the two layers.

Wiki: 3D structures lack documentation

The wiki section regarding 3D structures is empty. This is particular problematic for 3D valves, a type of component needed if the user is planning to fabricate using Neptune.

As a suggestion, I leave the following text that might be included in the wiki.

3D valves
This statement define entities both in the control (drawn in red) and flow (drawn in blue) layers.

• The presence of a 3D valve in the flow layer is similar to a node that accepts up to two connections: an input and an output. The valve will block or let pass liquid in the flow layer depending on whether its presence in the control layer has pressure or not.
• The presence of a 3D valve in the control layer has just one input expected to be connected to a liquid source in the that layer.

Important:

• 3DValves declarations need to specify orientation - horizontal or vertical - and that parameter defines the location of the input/output of the valve in the flow layer, and the input location for the part of the valve in the control layer. Check the figure.
• 3DValves declarations should be made in the flow layer section of a MINT file, and before declaring any channel connecting to them.

Make statement parameters declared in any order

Add Param for control port radii in Transposer Module

The current implementation of the Transposer does not take in a port radius parameter. This is causing problems with the design.

NODE declaration causes "out of index" errors

NODE something

causes the following error on fluigicad.org

Traceback (most recent call last):
  File "//.pyenv/versions/3.8.0/bin/fluigi", line 8, in <module>
    sys.exit(main())
  File "//.pyenv/versions/3.8.0/lib/python3.8/site-packages/fluigi/cmdline.py", line 165, in main
    size_nodes(current_device)
  File "//.pyenv/versions/3.8.0/lib/python3.8/site-packages/fluigi/pnr/utils.py", line 11, in size_nodes
    gedge = list(nbers)[0]
IndexError: list index out of range

MINT file:

DEVICE device

LAYER FLOW
PORT p1, p2, p3, p4, p5, p6 r=700;
PORT c1, c2, c3, c4 r=700;
PORT pw1, pw2, pw3, pw4 r=700;
PORT cw1, cw2, cw3, cw4 r=700;
PORT something r=700;
PORT n1, n2, n3 r=700;

NODE something;

METER m1, m3, m4, m5, m6, m6, m7, m8, m9, m10, m11, m12, m13, m14, m15, m16, m17, m18, m19 rotation=270 valveRadius=810 valveGap=395 flowChannelWidth=600 length=10710 width=11140;
METER m2 rotation=180 valveRadius=810 valveGap=395 flowChannelWidth=600 length=10710 width=11140;
MIXER mix1 rotation=90 channelWidth=600;
INCUBATOR inc1 rotation=90;
PUMP pu1, pu2, pu3, pu4, pu5 rotation=90 width=1200 flowChannelWidth=600;

CHANNEL ch1 from c1 to m1 1 w=600;
CHANNEL ch2 from p1 to pu1 1 w=600;
CHANNEL ch3 from pu1 2 to m1 2 w=600;
CHANNEL ch4 from m1 3 to cw1 w=600;
CHANNEL ch5 from m1 4 to pw1 w=600;
CHANNEL ch6 from m1 5 to mix1 1 w=600;

CHANNEL ch7 from p2 to pu2 1 w=600;
CHANNEL ch8 from pu2 2 to inc1 1 w=600;
CHANNEL ch9 from inc1 2 to mix1 1 w=600;

CHANNEL ch10 from mix1 2 to n1 w=600;
CHANNEL ch11 from p3 to n1 w=600;

CHANNEL ch12 from c2 to m2 1 w=600;
CHANNEL ch13 from p4 to pu3 1 w=600;
CHANNEL ch14 from pu3 2 to m2 2 w=600;
CHANNEL ch15 from m2 3 to cw2 w=600;
CHANNEL ch16 from m2 4 to pw2 w=600;
CHANNEL ch17 from m2 5 to n1 w=600;

CHANNEL ch18 from n1 to pu3 1 w=600;
END LAYER

Tree Unclear

It is unclear how trees work. How to connect ports/channels/valves directly to trees is unclear based off of the information given in the wiki. Trees in general just do not work.

Valve causes component error

When trying to add valves, I get a component error. Here is some test code to demonstrate this:

DEVICE covid_test_circuit

LAYER FLOW

PORT p1, p2 portRadius=700;
NODE n1;
CHANNEL c1 from p1 2 to n1 4 channelWidth=800;
CHANNEL c2 from n1 2 to p2 4 channelWidth=800;
END LAYER


LAYER CONTROL
PORT p3 portRadius=700;
VALVE v1 on c1 width=300 length=100;
VALVE v2 on c2 width=300 length=100;

NET net1 from p3 1 to v1 4, v2 4 channelWidth=50;

END LAYER

And here is the output:

output dir: /var/www/fluigicad.org/jobs/tmp__6083120dc4667500180b76b3/output
Running File: /var/www/fluigicad.org/jobs/tmp__6083120dc4667500180b76b3/MINT_example.uf
Creating the output directory:
Computing Constraints
Pulling Default Values of Components
Pulling Dimensions of Components
Pulling Terminals of Components
Setting Default MAX Dimensions to the device: (76200, 76200)
Starting terminal/port assignment ...
output: /var/www/fluigicad.org/jobs/tmp__6083120dc4667500180b76b3/output/covid_test_circuit.dot
Parsing Layers...
Layer 0:
Name - "FLOW_0"
ID - "0"
Type - "FLOW"
Group - "0"
Layer 1:
Name - "FLOW_0"
ID - "1"
Type - "CONTROL"
Group - "0"
Component - p1
  xpos - 0
  ypos - 0
  x-span - 1400
  y-span - 1400
  spacing - 1000
  Port - 1
    Port.x - 700
    Port.y - 700
Adding to FLOW ...
Component - p2
  xpos - 0
  ypos - 0
  x-span - 1400
  y-span - 1400
  spacing - 1000
  Port - 1
    Port.x - 700
    Port.y - 700
Adding to FLOW ...
Component - n1
  xpos - 0
  ypos - 0
  x-span - 800
  y-span - 800
  spacing - 1000
  Port - 1
    Port.x - 0
    Port.y - 0
Adding to FLOW ...
Component - p3
  xpos - 0
  ypos - 0
  x-span - 1400
  y-span - 1400
  spacing - 1000
  Port - 1
    Port.x - 700
    Port.y - 700
Adding to CONTROL ...
Component - v1
  xpos - 0
  ypos - 0
  x-span - 300
  y-span - 100
  spacing - 1000
  Port - 1
    Port.x - 150
    Port.y - 50
Adding to CONTROL ...
Component - v2
  xpos - 0
  ypos - 0
  x-span - 300
  y-span - 100
  spacing - 1000
  Port - 1
    Port.x - 150
    Port.y - 50
Adding to CONTROL ...
Connection - c1
  Source - p1
    Source Terminal - ERROR!!!!!!
  Sink - n1
    Sink Terminal - ERROR!!!!!!
  channelWidth - 800
  channelSpacing - 1600
Adding to FLOW layer ... 
Connection - c2
  Source - n1
    Source Terminal - ERROR!!!!!!
  Sink - p2
    Sink Terminal - ERROR!!!!!!
  channelWidth - 800
  channelSpacing - 1600
Adding to FLOW layer ... 
Connection - net1
  Source - p3
    Source Terminal - 1
  Sink - v1
    Sink Terminal - ERROR!!!!!!
  Sink - v2
    Sink Terminal - ERROR!!!!!!
  channelWidth - 50
  channelSpacing - 100
Adding to CONTROL layer ...
valve id: v1, connection id: c1
valve id: v2, connection id: c2
Firing Constructor for Placer
---------------Initial Placement Work-----------------
PAR Return code:-11
Traceback (most recent call last):
  File "//.pyenv/versions/3.8.0/bin/fluigi", line 8, in <module>
    sys.exit(main())
  File "//.pyenv/versions/3.8.0/lib/python3.8/site-packages/fluigi/cmdline.py", line 243, in main
    par_device = generate_device_from_parchmint(str(temp_parchmint_file))
  File "//.pyenv/versions/3.8.0/lib/python3.8/site-packages/fluigi/cmdline.py", line 80, in generate_device_from_parchmint
    return Device(device_json)
  File "/pybin/pyparchmint/parchmint/device.py", line 71, in __init__
    self.parse_from_json(json)
  File "/pybin/pyparchmint/parchmint/device.py", line 296, in parse_from_json
    self._valve_map[self.get_component(key)] = self.get_connection(value)
TypeError: unhashable type: 'Component'

Mint Wiki Diamond Rxn Chamber

Mint Wiki does not describe channel width and chamber width

Cell traps

Cell traps do not work in fluigi, might be a coding issue but we can't get them to appear on our final chip designs

Duplicate user-created modules/sections

For designs that require identical repeated sections, it would be helpful to have the ability to easily include multiple instances without copy-pasting many lines of code. A function that allows users to create their own module/group that they can have multiple instances of without coding individual lines would be super beneficial.

Ability to assign terminals to Portbank ports