[space] Unneeded space in ternaries about verible

[msfschaffner]

b/145170233

[fangism]

This case not handled, should be an easy fix.

Reduced test case:

module m;
assign r = a ? b : c;
endmodule

$ verilog_format -v=4 --alsologtostderr  ~/testing/verilog/formatting/b145170233.sv
...
I1125 18:50:51.146008   96624 token_annotator.cc:114] Spacing between SymbolIdentifier and ':'
I1125 18:50:51.146015   96624 token_annotator.cc:315] spaces: -1, reason: Default: spacing not explicitly handled
I1125 18:50:51.146022   96624 token_annotator.cc:320] Unhandled inter-token spacing between SymbolIdentifier and ':', defaulting to 1

By default, 'unhandled' cases preserve original spacing, which explains why you still see multiple spaces.