Related Issues (20)
- How to use rule for having a begin and end HOT 4
- Insufficient forbidden-macro documentation HOT 1
- The first macro get blamed for any syntax issues in the file
- smoke-test-analyzer currently not working.
- How can I parse only verilog and not systemverilog? HOT 1
- [Help or suggestion] How to disable short if-else statements on a single line? HOT 2
- [Feature request] Support to add spaces in parentheses/emptyblock/emptyparentheses with formatter
- Crash of formatter on a signed wire
- How to print original code real line number in ./print_modules.py or ./print_tree.py ?
- Formatter removes newline between successive ` directives HOT 4
- Migrate name style rules to regex HOT 4
- Rejected valid signal name HOT 4
- Potential crash when local file is replaced with verilog::VerilogProject::UpdateFileContents()
- strict weak ordering problem in autoexpander DependsOn()
- Comment influences line breaks in the following line
- uvm-macro-semicolon detects false positives HOT 3
- Property definition with disable iff before event fails
- typedef array of interfaces not supported
- [Feature request] Signal names in the module instantiation (align brackets and add spaces inside)
- How to debug VSCode LS? HOT 3
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