Comments (3)
Issue is here:
From what I have seen quickly looking at this, I think the only UVM macros that are verilog_tokentype::MacroIdentifier
are the ones ending in _end
, so we could add that extra check:
diff --git a/verilog/analysis/checkers/uvm_macro_semicolon_rule.cc b/verilog/analysis/checkers/uvm_macro_semicolon_rule.cc
index 3e7bc9d1..3eb445d7 100644
--- a/verilog/analysis/checkers/uvm_macro_semicolon_rule.cc
+++ b/verilog/analysis/checkers/uvm_macro_semicolon_rule.cc
@@ -55,11 +55,18 @@ static std::string FormatReason(const verible::TokenInfo ¯o_id) {
// Returns true if leaf is a macro and matches `uvm_
static bool IsUvmMacroId(const verible::SyntaxTreeLeaf &leaf) {
+ const absl::string_view text = leaf.get().text();
if (leaf.Tag().tag == verilog_tokentype::MacroCallId ||
leaf.Tag().tag == verilog_tokentype::MacroIdItem ||
leaf.Tag().tag == verilog_tokentype::MacroIdentifier) {
- return absl::StartsWithIgnoreCase(leaf.get().text(), "`uvm_");
+ const bool starts_with_uvm = absl::StartsWithIgnoreCase(text, "`uvm_");
+ if (leaf.Tag().tag == verilog_tokentype::MacroIdentifier) {
+ const bool ends_with_end = absl::EndsWithIgnoreCase(text, "_end");
+ return starts_with_uvm && ends_with_end;
+ }
+ return starts_with_uvm;
}
+
return false;
}
I'll try and see if there is a complete list of UVM macros somewhere to make sure this hack is OK although I guess we would prefer having false negatives rather than false positives on this check.
from verible.
False positives:
- UVM_DEFAULT_TIMEOUT
- UVM_MAX_STREAMBITS
- UVM_PACKER_MAX_BYTES
- UVM_REG_ADDR_WIDTH
- UVM_REG_DATA_WIDTH
- UVM_REG_BYTENABLE_WIDTH
- UVM_REG_CVR_WIDTH
- UVM_TLM_..._MASK
So I guess my proposed change is ok.
from verible.
Let me know if you find any other false positive!
from verible.
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from verible.