Comments (1)
I have a repo dedicated to highlighting SystemVerilog syntax in VS Code, which is still under development. However, it is sufficient for most use cases: https://github.com/hankhsu1996/vscode-better-systemverilog-syntax. This might be useful for the project. However, combining static syntax highlighting with semantic analysis yields the best results. I'm wondering if there are any plans for Verible to implement semantic highlighting?
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Related Issues (20)
- Formatter removes newline between successive ` directives HOT 4
- Migrate name style rules to regex HOT 4
- Rejected valid signal name HOT 4
- Potential crash when local file is replaced with verilog::VerilogProject::UpdateFileContents()
- strict weak ordering problem in autoexpander DependsOn()
- Comment influences line breaks in the following line
- uvm-macro-semicolon detects false positives HOT 3
- Property definition with disable iff before event fails
- typedef array of interfaces not supported
- [Feature request] Signal names in the module instantiation (align brackets and add spaces inside)
- How to debug VSCode LS? HOT 3
- The formatter combines the compiler directives into one line of code
- false-positive for CamelCase parameter in a SV module HOT 4
- Windows CI currently failing; wants chocolatey credentials ? HOT 3
- Tasks inside current file does not show up in the workspace symbol list
- Unexpected formatting of interface classes HOT 1
- VSCode LSP crashes while adding module inputs/outputs HOT 3
- Struct signals not checked for `signal-name-style`
- Generate default .rules.verible_lint from verible-verilog-lint HOT 2
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