exception vectors go to .data about riscv-dv

[taoliug]

This issue should be gone for the bare program mode.
For the data section address, the generated program is intended to be used for core level verification rater than SOC level, so it doesn't have any notion of memory space partition. I think this can be added by implement custom load/store instruction stream. For example, you can add label for each memory region, and use load/store to access these regions based on the region label + region address offset.

[agrobman]

We do core level verification , but the core includes internal memories, memory mapped interrupt controller we need to verify. L/S unit needs stimuli with mixed targets ...

[agrobman]

we also have a minimum MMU/MPU logic which defines memory characteristics based on address -
the LS transaction types differ depending it's I/O or just regular memory and we need to test these characteristics. The CPU RTL has various parameters, which define where these internal memories reside, so we have to tune code/data locations accordingly.

[taoliug]

Does the core support virtual address translation?

[agrobman]

It doesn’t, but we have plans for future versions. We’re also planning multithreaded cores with amo instructions for synchronization. From: taoliug <[email protected]> Sent: Friday, September 6, 2019 4:27 PM To: google/riscv-dv <[email protected]> Cc: Alexander Grobman <[email protected]>; Author <[email protected]> Subject: Re: [google/riscv-dv] exception vectors go to .data (#129) CAUTION: This email originated from outside of Western Digital. Do not click on links or open attachments unless you recognize the sender and know that the content is safe. Does the core support virtual address translation? — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub<#129>, or mute the thread<https://github.com/notifications/unsubscribe-auth/AK5G544DXNOGHPODWFYEEC3QILDJ5ANCNFSM4IULECIA>.

[taoliug]

Right now the the program generate many data pages with label : data_page_{idx}. The default setting is 40 4KB data pages. One easy way to achieve your goal is to link these pages to the various regions in your memory map, so that existing load/store instruction can access different regions naturally. Another way to do it to name the data pages in a more meaningful way. Like
{
region_0_name : 4KB
region_1_name: 16KB
region_2_name: 512B
....
}
In your link script, you can link each region to corresponding address. This will complicate the page table setup though.

[agrobman]

Don’t they all belong to the same .data section? As far as I know linker operates with sections, not labels. If you prepend your data pages with “.section dataN”, these pages can be relocated by linker to any address independently – Interesting useful feature could be to use the generator to select physical addresses for these pages … ( I think, there is special .section format to define start address, like .org XXXX command) From: taoliug <[email protected]> Sent: Friday, September 6, 2019 4:36 PM To: google/riscv-dv <[email protected]> Cc: Alexander Grobman <[email protected]>; Author <[email protected]> Subject: Re: [google/riscv-dv] exception vectors go to .data (#129) CAUTION: This email originated from outside of Western Digital. Do not click on links or open attachments unless you recognize the sender and know that the content is safe. Right now the the program generate many data pages with label : data_page_{idx}. The default setting is 40 4KB data pages. One easy way to achieve your goal is to link these pages to the various regions in your memory map, so that existing load/store instruction can access different regions naturally. Another way to do it to name the data pages in a more meaningful way. Like { region_0_name : 4KB region_1_name: 16KB region_2_name: 512B .... } In your link script, you can link each region to corresponding address. This will complicate the page table setup though. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub<#129>, or mute the thread<https://github.com/notifications/unsubscribe-auth/AK5G547T2IJVFOYEFFAVLO3QILELFANCNFSM4IULECIA>.

[taoliug]

Let me give a try for the custom region setting. Use .org might be a better idea as it reduce the complexity of the link script.
{
data_section_0_name ,0x0001_0000, 4KB, instruction
data_section_1_name ,0x0002_0000, 16KB, data
data_section_2_name ,0x0003_F000, 16KB, data
....
}

[agrobman]

Link script can use something like {data* } => .data to put all dataN sections to one output .data section to emulate current behavior ( I don’t remember exact syntax). From: taoliug <[email protected]> Sent: Friday, September 6, 2019 4:53 PM To: google/riscv-dv <[email protected]> Cc: Alexander Grobman <[email protected]>; Author <[email protected]> Subject: Re: [google/riscv-dv] exception vectors go to .data (#129) CAUTION: This email originated from outside of Western Digital. Do not click on links or open attachments unless you recognize the sender and know that the content is safe. Let me give a try for the custom region setting. Use .org might be a better idea as it reduce the complexity of the link script. { data_section_0_name ,0x0001_0000, 4KB, instruction data_section_1_name ,0x0002_0000, 16KB, data data_section_2_name ,0x0003_F000, 16KB, data .... } — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub<#129>, or mute the thread<https://github.com/notifications/unsubscribe-auth/AK5G544YSIHTMWCDZ64IKEDQILGMFANCNFSM4IULECIA>.

[taoliug]

The main complexity comes from setting up page tables for these scattered data pages. Especially if we want to inject error in the page table entry and do error recovery. I need to think about a clean way to do it. Right now the assumption is that all pages are equal size and continuously allocated in memory space. I think it makes sense to allow user customize the page location/size/access_type.

[agrobman]

I agree it’s not simple .. we have 4 data pointers in our tests – one for internal data memory, another for external “normal” , one – for I/O type external and one for our internal I/O. Our test gen mixes L/S instructions with all these pointers in the instruction streams . Limitation is that we had to reserve 4 GPRs for these pointers and accesses can go to 4KB windows only. To check address aliasing effects it may be not sufficient, especially if the CPU includes data cache . ( we don’t have DC, though) Other L/Ss with random addresses can be created with a sequence, setting up data pointer, but then it’s too deterministic, one more possibility is to get data pointers from memory tables – to check L/L or L/S dependencies From: taoliug <[email protected]> Sent: Friday, September 6, 2019 5:28 PM To: google/riscv-dv <[email protected]> Cc: Alexander Grobman <[email protected]>; Author <[email protected]> Subject: Re: [google/riscv-dv] exception vectors go to .data (#129) CAUTION: This email originated from outside of Western Digital. Do not click on links or open attachments unless you recognize the sender and know that the content is safe. The main complexity comes from setting up page tables for these scattered data pages. Especially if we want to inject error in the page table entry and do error recovery. I need to think about a clean way to do it. Right now the assumption is that all pages are equal size and continuously allocated in memory space. I think it makes sense to allow user customize the page location/size/access_type. — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub<#129>, or mute the thread<https://github.com/notifications/unsubscribe-auth/AK5G54YLD2IKQMIZ5ZNV5DTQILKOTANCNFSM4IULECIA>.

[agrobman]

to my original complain - when you place code(exception handlers in this case) to data sections it confuses some tools
objdump for ex - it won't disassemble data sections. You can always place it in the code, by prepending it with .text - assembler collects all .text code from source to one .text section in obj file

you can have sections in the source file as layered cake:
.text
some code
.data
some data
.text
another code
.data
another data

at output all .text will be collected together and and all .data together too, forming one .text and one .data

[taoliug]

yes, this issue should have been fixed by this change.
68243cc#diff-f4e7ea3a932515dd6de98542c6c9754bR177

.text
user program
.data
user data
.text << this is missing
kernel program
.data
kernel data

[agrobman]

why it is section text.init and not just .text?

.macro init
.endm
.section .text.init <<<< ????
.globl _start
_start:

[taoliug]

I think this is inherited from riscv-tests, it's used by link script to link this section to beginning of the program. Maybe for your use case, you want it to be .text so that you can have your own init section?

[agrobman]

Yes, I had to change manually this one to .text .. From: taoliug <[email protected]> Sent: Friday, September 6, 2019 6:31 PM To: google/riscv-dv <[email protected]> Cc: Alexander Grobman <[email protected]>; Author <[email protected]> Subject: Re: [google/riscv-dv] exception vectors go to .data (#129) CAUTION: This email originated from outside of Western Digital. Do not click on links or open attachments unless you recognize the sender and know that the content is safe. I think this is inherited from riscv-tests, it's used by link script to link this section to beginning of the program. Maybe for your use case, you want it to be .text so that you can have your known init section? — You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub<#129>, or mute the thread<https://github.com/notifications/unsubscribe-auth/AK5G54YSH32SBLVR7K2AQLDQILR3FANCNFSM4IULECIA>.

[taoliug]

With above changes, now each memory region as it's own section, You can link them to match the memory map. Memory region can be configured in the config class:
https://github.com/google/riscv-dv/blob/master/src/riscv_instr_gen_config.sv#L79
For the external memory, I'd suggest to specify a small range for simulation purpose, otherwise it might take a long time to randomly init the memory region.

[Nr] Name Type Address Offset
Size EntSize Flags Link Info Align
[ 0] NULL 0000000000000000 00000000
0000000000000000 0000000000000000 0 0 0
[ 1] .text PROGBITS 0000000080000000 00001000
000000000000a2ac 0000000000000000 AX 0 0 4096
[ 2] .tohost PROGBITS 000000008000b000 0000c000
0000000000000048 0000000000000000 WA 0 0 64
[ 3] .region_0 PROGBITS 000000008000c000 0000d000
0000000000001000 0000000000000000 WA 0 0 1
[ 4] .region_1 PROGBITS 000000008000d000 0000e000
0000000000004000 0000000000000000 WA 0 0 1
[ 5] .region_2 PROGBITS 0000000080011000 00012000
0000000000002000 0000000000000000 WA 0 0 1
[ 6] .region_3 PROGBITS 0000000080013000 00014000
0000000000000200 0000000000000000 WA 0 0 1
[ 7] .region_4 PROGBITS 0000000080013200 00014200
0000000000001000 0000000000000000 WA 0 0 1
[ 8] .user_stack PROGBITS 0000000080014200 00015200
0000000000009c40 0000000000000000 WA 0 0 64
[ 9] .kernel_stack PROGBITS 000000008001de40 0001ee40

[agrobman]

any idea, why am I getting region sections with zero data?
.pushsection .region_0,"aw",@progbits;
region_0:
.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
.word 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000

[taoliug]

Because there are three data patterns for the data section
https://github.com/google/riscv-dv/blob/master/src/riscv_instr_pkg.sv#L616

typedef enum bit [1:0] {
RAND_DATA = 0,
ALL_ZERO,
INCR_VAL
} data_pattern_t;

[agrobman]

Is the data pattern randomly selected?

[agrobman]

One more thing

can you add _finish: label to the _exit, something like this:

_exit:
_finish:
j write_tohost

[agrobman]

one more idea:
print a sequence name before and after it is injected as a comment into the generated source

[eroom1966]

Hi All
I was following this thread, and wondering if the best method is the tohost/fromhost idea.
I cannot recall whom, but I am pretty sure there has been talk regarding dropping the whole tohost/fromhost interface, in which case the ecall would seem the best approach.
If we were to simply follow the linux syscall style, we could test the syscall number, eg exit()
it would be trivial then to write a traphandler which interrogates the syscall number and does the appropriate action
@agrobman can I ask what is your execution environment which need to have the specific labels in the elf file to detect an END-OF-TEST scenario ?
Thx
Lee

[taoliug]

One more thing

can you add _finish: label to the _exit, something like this:

_exit:
_finish:
j write_tohost

Can you extend riscv_asm_program_gen::gen_program_end to add this? I don't want to add TB specific logic in the upstream code.

[taoliug]

I am closing this issue for now as I believe the original issue is solved. Please file a different issue for other feature requests. Thanks.

[taoliug]

one more idea:
print a sequence name before and after it is injected as a comment into the generated source

This is already implemented:

                  slt        a4, a6, a3
                  lbu        a6, 33(ra) #end riscv_hazard_instr_stream_5
                  la         s9, region_4+319 #start riscv_hazard_instr_stream_11
                  lh         t2, 59(s9)

[agrobman]

@eroom1966 , _finish label is used by our RTL verification environment .
we don't like ecall/syscall as end of test because we need to verify this instruction in randoms by itself .
Also some benchmarks use syscall to interact with host - we utilize this interface when run these benchmarks on the RTL model ..