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Even in flatten netlists, top-level input and output can be multi-bit PORTS which drive/load a BUS. To support this feature, need to add new nlNode object types. A PORT should be a group of PIN objects and a BUS should be a group of NET objects.

Currently, lib cells and the netlist need to be described in Python. Adding the ability to read the lib cells from liberty files and reading a verilog netlist will reduce the extra work required.