This is my first significant project in cadence, completed in my third year of BE. I advise you to watch "Prof Nagendra Krishnapura" lectures from IITM on "Analog IC Design" to gain a better grasp of the implementation. I learned about the fundamentals and significance of feedback systems in these lectures and designed a two stage opamp with Miller compensation and a nulling resistor.
For the design formulas of the transistors I referred to textbook by P. Allen and D. Holberg,"CMOS Analog Circuit Design",The Oxford Series in Electrical and Computer Engineering, 3rd ed these are easily available online
I have given the complete detailed Circuit analysis of the opamp in this folder ---> CIRCUIT ANALYSIS
Gain= 70db
Slew rate = 10 V/uS
GBW (Gain Bandwidth) = 30M Hz
ICMR(+)= 1.0 V
ICMR(-)= 300 mV
Vdc = 1.2 V
Cl (Load Capacitance) = 1pF
The final circuit of the opamp which includes all the differntial pair and current mirror including dummy transistors which were used during the implementation of layout.
Note:
Initially the phase margin obtained for 5pF was not in a satisfactory range.
Therefore I added a resistor in feedback so it can bring back RHP Zero to some extent.
I decided the value of resistor by running a simple AC analysis. However,This is not a conventional method of designing a nulling resistor
The Gain obatined was around 68db with a Unity gain Bandwidth of 23M Hz for a load of Cl=1pf with a phase margin of 80 degrees which is pretty identical comparing
for the designed specification:
Av=68db
GBW=23M Hz
Cl =1pf
Phase Margin =78 degree
However considering for the worst case operation whenever there is a greater output load at the opamp.
As the load essentially increases the frequency of operation of the design reduces thereby
we need to check if the opamp becomes unstable (ie) if the phase margin becomes less than 45 degree at GBW
So I replaced the Capactive load to 5pf to measure the phase margin and GBW of the opamp
With the help of AC analysis we can see that with greater load the gain remains the same however the unity gain bandwidth is decreased From 23M Hz to 18M Hz.
Av=68db
GBW=18M Hz
Cl =5pf
Phase Margin =80 degree
Slew rate is one of the major characteristics of opamp , In an ideal opamp the slew rate is infinite however it is not possible for a infinite
slew rate in pratical cases.
To find the slew rate first we need to implement a regular voltage follower as shown below :
We can find the slew rate of opamp with the help of transient analysis by calculating the rate of change of output with the help of waveforms obtained
Slew rate = dVo/dt
Slew rate = 999 mV/111 n S = 9 V/uS
Therefore the obtained slew rate of the opamp was found out to be 9 V/uS which is extremely close to that of the our designed specification of 10 V/uS
CMRR is ability of the opamp to reject common mode signals , As common mode gain Av(Cm)=0 the CMRR is ideally infinite CMRR is given by CMRR= Av(DM)/Av(Cm) ie (Differrential Mode gain to that of Common mode gain)
CMRR(db)= log(Av(DM))-log(Av(CM)) (db)
As we know the diifferntial mode gain of opamp was found out to be 68db, we can find the common mode gain by providing the common input to both
the terminals of the Opamp.
From the above diagram is noted that Common mode gain AV(Cm)=-14db
Therefore
CMRR = 68.4-(-14.3) CMRR = 82.7 db
Therefore the Common mode rejection ratio was found out to be 83 db which is pretty good, Ensuring that it rejects common mode signals to good extent
Opamp the name itself indicates it is used to perform operation on signals such as addition,subtraction and more
So let us verify some basic operation with the opamp created
These are the most basic operation which could be done using an op amp. Voltage follower is where output follows the input and comparator produces an output +Vsat or -Vast relative to inputs (Vp-Vn)
Circuit shows a voltage follower on the first stage followed by a comparator stage , As +Vast =1.2V and -Vsat =0 the voltage follower is clipped off accordingly
Implementation and veification of 4bit R2R DAC was done using th e designed opamp and was tested for it working with the help of waveforms by running a transient analysis
Waveform obtained :
Non Inverting integrator circuit explaination is easily available online, Please refer to those if you dont understand the circuit
Waveform obtained :
Gain= 68db
Slew rate = 9 V/uS
GBW (Gain Bandwidth) = 23M Hz
ICMR(+)= 0.8 V
ICMR(-)= 300 mV
Vdc = 1.2 V
Cl (Load Capacitance) = 1pF-5pF
In Analog circuits, designs are used like differential pairs and current mirrors, where the matching of device characteristics such as the threshold voltage Vt is important.
If device threshold differences of a few millivolts or less can determine the difference performance and yield of a design. Threshold voltage also varies due to the variations in the number of doping atoms or process variation. For that, we need to match the analog devices
Common Centriod matching technique was used for the differntial pairs. It requires absolute symmetricity along both folded X and Y axis
of the layout.
The Block level implementation of the common centroid method used was as below
If $ is the process variation which occurs ,considering it across both the axis tranistor A and B can have a process variation of upto 7$ , It is such that both of the transistor undergo same mismatch so that they remain identical.
The differntial pair was surrounded by a P-tap Guard Ring Across it and waas connected to VDD , and was ensured symmetricity was maitained throughout the Common Centriod block.
Dummy transistors were surrounded across the differential pairs on both of the axis, to further protect from process variation.
Interdigitation matching techniques wre used for implementation of both NMOS and PMOS current mirrors, Interdigitation process ensures to Overcome come mismtach in single orientation axis Interdigitation also reqires symmetricity with respect to centre of its axis.
If $ is considered as the process variation which occurs as Guass distribution , Then according to the above layout both of the transistor would have a total process varation of 14$. The PMOS current mirror was surrounded by Ntap guard ring and NMOS current mirror was surrounded by Ptap Guard Ring and was ensured that symmetricity was maintained across it.
Dummy transistors were added at the end of each of side of the current mirrorsto further protect from process variation
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