It is an IIR filter implemented by verilog. The inputs include clock, reset, data_in and data_done, while the outputs include address of the data, read enable, write enable, data and finish. I use three states to process this program: IDEL, COUNT and WRITE.
In the IDEL state, we do nothing but initialize all the variables. In the COUNT state, the filter reads the data, chooses the weight to product and operates to get the value. In the WRITE state, the filter just comfirms if all the variables are initialized. Also, It writes back the operated data to the RAM.
Note: there is more than one way to operate IIR filter. You can choose more effecient way to do this, but the price is using more hardware. Whatever, better effeciency costs more, less hardware means less effeciency.