camrbuss / gol-ice40-hub75

Learning experience - Conway's Game of Life implemented in Verilog on a ICE40 with a Hub75 LED Panel

gol-ice40-hub75

Learning experience - Conway's Game of Life implemented in Verilog on a ICE40 with a Hub75 LED Panel ☀️

Hardware

• iCESugar iCE40UP5K development board 🤖
• Hub75 64 x 64 P3 RGB Matrix with 1/32 scan 💡
• 1 BIT SQUARED PMOD Tri State Transceiver 🔌

Verilog Structure

The general philosophy was to avoid using any inputs and to have the entire code in one module to keep it extremely simple. Game of Life is played on all 4096 pixels and is output on all color channels to show up as white. There are plenty of inefficiencies and bad practices here, but it works 🤷

In general it takes about 128 clock cycles to preload the matrix with values and about 5000 cycles to determine the next state of the game. With a 24MHz clock speed, this means there is a brief blank period, but in general the "speed" of the game up to about 2000 game cycles a second. This speed could be greatly improved if BRAM was used instead of SPRAM, but currently the Yosys BRAM inference for the iCE40 was not behaving.

top.v

1. Write the preload data into os_t_spram and os_b_spram for the top and bottom halves of the display. Each address contains 1/4 of a row

Address  0                1                2                3
Data     1111111111111111 1111111111111111 1111111111111111 1111111111111111
Address  4                5                6                7
Data     1111111111111111 1111111111111111 1111111111111111 1111111111111111

2. Move the os_*_spram data into ns_spram where on the first bit of each address is used. This means we are using 4096 address locations
3. Use the ns_spram addresses to get the state of the current cell and all eight neighbors
4. Determine if the cell should live or die based on it's neighbors state and then write its state into os_*_spram to be displayed.

top_tb.v

To use the test bench with Icarus Verilog you will need to switch the 24 MHz clock to a clk generated by the test bench as the simulation of the pll does not generate a clock. Other than the clock there are no other inputs.

Make sure that you have the SPRAM simulation in the Yosys cells_sim.v The Makefile is currently hard coded to the location below.

/usr/local/share/yosys/ice40/cells_sim.v

Convert to 12MHz clock for use with test bench

sed -i 's/posedge clk_24mhz/posedge clk/g' top.v
sed -i 's+// input clk,+input clk,+g' top.v
sed -i 's+CLOCK(clk_24mhz)+CLOCK(clk)+g' top.v

Convert to 24MHz clock for use with hardware

sed -i 's/posedge clk/posedge clk_24mhz/g' top.v
sed -i 's+input clk,+// input clk,+g' top.v
sed -i 's+CLOCK(clk)+CLOCK(clk_24mhz)+g' top.v

Current Device Utilization

Info: Device utilisation:
Info:            ICESTORM_LC:  1615/ 5280    30%
Info:           ICESTORM_RAM:     0/   30     0%
Info:                  SB_IO:    14/   96    14%
Info:                  SB_GB:     7/    8    87%
Info:           ICESTORM_PLL:     1/    1   100%
Info:            SB_WARMBOOT:     0/    1     0%
Info:           ICESTORM_DSP:     0/    8     0%
Info:         ICESTORM_HFOSC:     1/    1   100%
Info:         ICESTORM_LFOSC:     0/    1     0%
Info:                 SB_I2C:     0/    2     0%
Info:                 SB_SPI:     0/    2     0%
Info:                 IO_I3C:     0/    2     0%
Info:            SB_LEDDA_IP:     0/    1     0%
Info:            SB_RGBA_DRV:     0/    1     0%
Info:         ICESTORM_SPRAM:     3/    4    75%

CAD

A 3d printable foot that inclines the hub75 is included in the cad directory. If you print it, make sure to mirror the part for each side.