The VectorBlox MXP Matrix Processor is an FPGA-based soft processor capable of highly parallel execution. Programmed entirely in C/C++, the MXP is capable of executing data-parallel software algorithms at hardware-like speeds. MXP's parameterrized design lets the user specify the amount of parallelism required, ranging from 1 to 128 or more parallel ALUs. Key features of the MXP include a parallel-access scratchpad memory to hold vector data and a high-throughput DMA engine.
VectorBlox Computing licenses the MXP processor as a synthesizable IP core for use in FPGA designs.
This preview release is for evaluation only, and consists of:
- Pre-built bitstreams to evaluate the MXP processor on several popular Altera and Xilinx FPGA development boards
- The MXP Software Development Kit (SDK)
- Example programs
- Documentation
To get started immediately:
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Ensure you have one of the supported development boards.
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Download the latest release zip file Full / Simulator Only).
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Follow the VectorBlox MXP Hardware & Software Quickstart for Quartus / Vivado / Simulator
For further VectorBlox MXP documentation, refer to the following:
There are several breaking changes to the API since between the 2017 and 2018 releases. Below is an overview of the changes, please see the Programming Reference (link above) for more details on the current API.
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Vector Shifts are srca >> srcb rather than srcb>> srca. This leads to some issues with shifting by scalar values which can be resolved by mapping shifting by scalar values to VMUL, and VMULH for shifting left and right respectively.
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All vector instructions are 3 dimensional, to do 1 or 2 dimensional instructions set nmats and/or nrows to 1. Because of this the
vbx_set_vl
,vbx_set_2D
, andvbx_set_3D
have changed. They now all accept 3 arguments. -
Destination, source A and source B all have independant sizes and signedness.
For further information please email us at [email protected] or visit http://www.vectorblox.com.