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Patricio Bulic's Projects

riscy icon riscy

Simple RISC-V RV32I CPU in VHDL for use in FPGA Designs

snn-fpga icon snn-fpga

Spiking Neural Network RTL Implementation

spikingneuralnet icon spikingneuralnet

Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons

squarers icon squarers

Approximate squarers, VHDL source, synthesis reports from standard cell library and 0.25 um CMOS process parameters

stm32-dht11 icon stm32-dht11

Interrupt safe driver for the DHT11 temperature/humidity sensor

tcas-stdp icon tcas-stdp

IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures

tinyodin icon tinyodin

tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.

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