brianbennett / fpga_nes

FPGA-based Nintendo Entertainment System Emulator

fpga_nes is an fpga-targeted Nintento Entertainment System emulator written in Verilog. It is currently under development, and is most notably missing support for mappers and the DMC sound channel. At this point, it runs most NROM games capably (e.g., Super Mario Brothers, Excitebike).

In addition, this project includes a C++ Windows application called NesDbg, which communicates with the FPGA over USB UART to load ROMs, run unit tests, readwrite memory, etc.

Hardware Setup:

1. Nexys 3 Spartan-6 FPGA board. ($119 / $199)
2. Micro-USB connection for FPGA power and programming.
3. VGA display connection for NES video output.
4. Micro-USB connection for communication between NES and NesDbg software.
5. PmodBB Bread Board for a solderless joypad connection. ($20)
6. NES Joypad Adapter to accept input from joypads. ($5)
7. 2 NES Joypads to accept user input. (2 * $5)
8. PmodAMP1 to amplify NES PWM audio output. ($20)
9. Speaker to play the NES sound. ($6)

Development Environment:

1. ISE 14.1 WebPack (free)
2. Visual Studio 2010 Express (free)

fpga_nes's Issues

Add configurable COM port for NesDbg

Currently hardcoded to COM5.

Soccer

Corruption in the top status bar during scrolling.

1942

Corruption. Missing letters in overlay text, mild flickering.

IRQs need to honor P register's interrupt disable bit

Add progress bar in NesDBG for ROM loads

Implement monochrome mode

Implement SRAM controller

Use SRAM as storage for carts instead of blockram. This is the first step toward supporting non NROM mappers.

Improve CPU/PPU timing correlation

Once using a BRAM framebuffer, try to get CPU and PPU timings to exact match of original NES.

Othello

Hang before title screen come up.

Upgrade to ISE 14.1

Implement alternate path for uploading cart data

Currently uses normal path used by CPU to write memory. In order to support mappers, it should load to physical banks instead of mapped addresses.

Frame capture, ROM test automation

Once BRAM framebuffer is supported, add support for frame capture and NesDbg support for automated testing of ROMs.

Reset pulse channel sequencer on write to $4003/$4007

Implement RGB emphasis bits

Implement switchable support for real/fake joypads.

Real NES controllers appear to have opposite signal polarity of imitation.

Fix BRK implementation

As implemented, BRK currently halts the machine for examination by NesDBG instead of causing an IRQ interrupt. Fix this, and update all tests to use one of the unofficial HLT opcodes instead of BRK.

BRAM frame buffer support

Instead of computing pixel color as they are outputted, ppu should compute pixel color and dump into a "back buffer" in block ram. This will enable a couple nice things:

Perfect PPU timings. Currently the PPU timings are kind of close, but are based on the VGA signal requirements. By decoupling the color generation and the display, the color generation should be able to work at a different clock than the display.

Frame capture for automated testing.

SMB flagpole sound effect

Pitch doesn't slide as high as it should.

Auto input for test automation

Allow NesDbg lua scripts to send controller input to the fpga.

Implement unofficial opcodes

Refactor apu_div to remove internal period regs, remove apu_div_const

Increase baud rate of UART connection.

Figure out why cpumc unit test fails at over 19200 bps.

Fix APU "jitter"

Writes to $4017 should take effect between 1 and 2 APU cycles later.

Mach Rider

Obvious corruption during demo.

Use smarter sequence generator for pulse duty cycle

IRQ Interrupts should be level based

Currently detecting falling edges; this shouldn't be necessary. Reset, too?

Fix sprite DMA timing

Sprite DMAs finish much too quickly, should match original NES timing.

Always double resolution

Remove resolution doubler option, and force it always on. Timing is way off for non-doubled screens now, and there's no good reason to fix it.

Fix $4017 write behavior to clock appropriate frame counter signals

unknown error initiaizing com5

hi，I run directly ise generate bit file, and then open the serial port, set 38400, ODD, ONEBITSTOP, NONE, last run nesdbg of after on display Unknown Error initiaizing com5, Do you know what this is reason?

Use shared CPU pulse between 6502 core and APU

Slalom

Corruption during demo once turning starts.

IRQ should push a B value of 0.

Hookup frame counter IRQ generation