belohoub / advanced-physical-design-using-openlane

Notes to the Advanced Physical Design using OpenLANE

Advanced Physical Design using OpenLANE/Sky130 Workshop Notes

• efabless-sponsored VSD-IAT workshop (2022-08-03 to 2022-08-07)

Table Of Contents

• Toolchain installation
• Workshop Day 1
  • The OpenLane-driven Design Flow
  • Synthesis in OpenLane
• Workshop Day 2
  • Floorplaning
    • Pin placement and logical cell placement blockage
  • Floorplan in OpenLane
  • Placement in OpenLane
  • Cell Characterization
• Workshop Day 3
  • Inverter ngSPICE Simulations
  • CMOS Fabrication Process
  • Tech File Labs
• Workshop Day 4
  • Standard Cell Layout to LEF
  • Timing Settings for Synthesys
  • Post-Synthesys Timing Analysis - Custom Execution
  • Clock Tree Synthesis
  • Timing analysis inside OpenLANE
• Workshop Day 5
  • Power Distribution Network
  • Global and Detail Routing
  • Standard Parasitic Exchange Format (SPEF) File
• References
• Credits

Toolchain installation

• Prior the workshop, I already have an experience with qflow

• I choose NOT to use the remote lab system and rather install tools on my private Debian machine to go through the complete process

• Prerequisities:

$ apt install -y build-essential python3 python3-venv python3-pip
...
$

• Docker installation instructions:
• openLane:

$ cd ${PROJ_WORK}/tmp/
$ mkdir openLane
$ git clone https://github.com/efabless/OpenLane.git .
...
$ # Checkout the latest release: mpw-4
$ git checkout 4a1c799
$ make
...
$ make test
...
[SUCCESS]: Flow complete.
Basic test passed
$ 

Workshop Day 1

The OpenLane-driven Design Flow

Synthesis in OpenLane

$ make mount
OpenLane Container (4a1c799):/openlane$ ./flow.tcl -interactive

[INFO]: 
         ___   ____   ___  ____   _       ____  ____     ___
        /   \ |    \ /  _]|    \ | |     /    ||    \   /  _]
        |   | |  o  )  [_ |  _  || |    |  o  ||  _  | /  [_
        | O | |   _/    _]|  |  || |___ |     ||  |  ||    _]
        |   | |  | |   [_ |  |  ||     ||  _  ||  |  ||   [_
        \___/ |__| |_____||__|__||_____||__|__||__|__||_____|


[INFO]: Version: mpw-4
[INFO]: Running interactively
% # load package
% package require openlane 0.9
0.9
% # prepare design - strating withthe existing design AES128
% prep -design aes128
...
[INFO]: Preparation complete
% run_synthesis
...
[INFO]: Synthesis was successful
% # AES128 verilog was synthesised and mapped by Yosys/ABC
% #   - number of std cells is 46009
% #   - number of DFF is 5568
% #   - optimal area is 455210 um2
% #   - optimal area is 455210 um2
% # AES128 STA: (-> no violations)
% #   - worst setup slack is 3.39ns
% #   - worst hold slack is 0.1ns
% #   - clock skew is 3.39ns
% exit
OpenLane Container (4a1c799):/openlane$ exit

Workshop Day 2

Floorplaning

• Wafer - contains many Dies
• Package - contains a single die
• Die - contains the logic and something like the "technological frame" for e.g. pads
• Core - contains the implemented IC logic

Pin placement and logical cell placement blockage

Floorplan in OpenLane

$ cd openLane/designs/aes128
$ # edit variables for the floorpanning step
$ editor sky130A_sky130_fd_sc_ms_config.tcl
...
$ cd ${PROJ_WORK}/tmp/openLane
$ make mount
OpenLane Container (4a1c799):/openlane$ ./flow.tcl -interactive -design aes128 -tag RUN_2022.08.04_07.33.37

% run_floorplan
...
1
% exit
OpenLane Container (4a1c799):/openlane$ exit

• Inspect the floorplan:

$ cd ${PROJ_WORK}/tmp/openLane/designs/aes128/runs/RUN_2022.08.04_07.33.37/results/floorplan
$ magic -T ${PROJ_WORK}/tmp/openLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read aes128.def

Placement in OpenLane

$ make mount
OpenLane Container (4a1c799):/openlane$ ./flow.tcl -interactive -design aes128 -tag RUN_2022.08.04_07.33.37

% run_placement
...
% exit
OpenLane Container (4a1c799):/openlane$ exit

• Inspect the layout:

$ cd ${PROJ_WORK}/tmp/openLane/designs/aes128/runs/RUN_2022.08.04_07.33.37/results/placement
$ magic -T ${PROJ_WORK}/tmp/openLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read aes128.def

Cell Characterization

Workshop Day 3

• as I've experience with this part of workshop, I mostly reviewed the theory provided by EDU videos.

Inverter ngSPICE Simulations

CMOS Fabrication Process

• mostly covered by the equal [Udemy curse](VSD - Custom Layout) I already had
• Standard cell design and characterization using openlane flow by nickson-jose

Tech File Labs

• Magic switch the set of DRC rules

% drc style drc(fast)
% drc style drc(full)
% drc check

Workshop Day 4

Standard Cell Layout to LEF

• the cell height must comply with power grid

• the cell width should be an odd multiple of the minimum grid

• the cell port must be at the intersection of the grid lines

• grid parameteres from the pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info file:

li1 X 0.23 0.46
li1 Y 0.17 0.34
met1 X 0.17 0.34
met1 Y 0.17 0.34
met2 X 0.23 0.46
met2 Y 0.23 0.46
met3 X 0.34 0.68
met3 Y 0.34 0.68
met4 X 0.46 0.92
met4 Y 0.46 0.92
met5 X 1.70 3.40
met5 Y 1.70 3.40

• synthesis/mapping library example: pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib

Timing Settings for Synthesys

• The following env. variables could be tuned:

SYNTH_STRATEGY
SYNTH_BUFFERING
SYNTH_SIZING

Post-Synthesys Timing Analysis - Custom Execution

• /scripts/base.sdc file is the sdc template
• pre_synth.conf config file example:

set cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um
read liberty -max PATH_TO/sky130_fd_sc_slow.lib
read liberty -min PATH_TO/sky130_fd_sc_fast.lib
read verilog ${PROJ_WORK}/tmp/openLane/designs/aes128/runs/RUN_2022.08.04_07.33.37/results/synthesis/aes128.v
link design aes128
read sdc path_to_my_updated_base.sdc
report checks -path_delay min_max -fields {slew trans net cap input_pin}
report_tns
report_wns

• run OpenSTA:

$ sta pre_synth.conf

• replace "bad" cell manually:

% # This is OpenSTA command line
% replace cell <cell_num> <new_cell_name>
% report_checks -from <node> -to <node> -through <node>
% report_tns
% report_wns
% report_checks -fields {net cap slew input_pin}
% write_verilog <netlist>

• now let's return to OpenLane and continue with P&R

Clock Tree Synthesis

• in OpenLane:

% run_cts

• CTS results were written to openlane/designs/aes128/runs/RUN_2022.08.04_08.32.49/results/cts/aes128.v

Timing analysis inside OpenLANE

• first create database for OpenRoad:

% openroad
...
openroad> read_lef <lef_file>
openroad> read_def <def_file>
openroad> write_db <db_file>
...
openroad> exit
...
openroad> read_db  <db_file>
openroad> read_verilog <synthetized_verilog>
openroad> read_liberty -max $::env(LIB_MAX)
openroad> read_liberty -min $::env(LIB_MIN)
openroad> read_sdc <sdc_file>
openroad> set_propagated_clock [all_clocks]
openroad> report_checks -path_delay min_max -format full_clock_expanded -digits 4

Workshop Day 5

Power Distribution Network

% gen_pdn
...
[INFO]: PDN generation was successful.
[INFO]: Changing layout from /openlane/designs/aes128/runs/RUN_2022.08.04_08.32.49/results/cts/aes128.def to /openlane/designs/aes128/runs/RUN_2022.08.04_08.32.49/tmp/floorplan/31-pdn.def
% 

$ /usr/local/bin/magic -T ../../../../pdks/sky130A/libs.tech/magic/sky130A.tech lef read tmp/merged.lef def read tmp/floorplan/31-pdn.def

Global and Detail Routing

% echo $::env(CURRENT_DEF)
/openlane/designs/aes128/runs/RUN_2022.08.04_08.32.49/tmp/floorplan/31-pdn.def
% set ::env(CURRENT_DEF) /openlane/designs/aes128/runs/RUN_2022.08.04_08.32.49/tmp/floorplan/31-pdn.def
/openlane/designs/aes128/runs/RUN_2022.08.04_08.32.49/tmp/floorplan/31-pdn.def
% set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
1
% set ::env(ROUTING_OPT_ITERS) 128
128
% set ::env(DETAILED_ROUTER) tritonroute
tritonroute
% run_routing

Standard Parasitic Exchange Format (SPEF) File

• SPEF file generation by using the SPEF_EXTRACTOR

$ cd <SPEF_EXTRACTOR_path>
$ python3 main.py <lef_file> <def_file>

• in the new version of the flow, the extractor is already included and it is automatically invoked at the end of the routing stage

References

• OpenLANE

Credits

• VLSI System Design
• efabless
• opencircuitdesign.com