Comments (2)
Hi. Please go to hw/readme.md for guide on regenerating the vivado project.
I’ll update the project description
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Thanks
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Related Issues (20)
- [BD 5-216] VLNV <xilinx.com:hls:FC_CIF_0_1:1.0> is not supported for the current part. HOT 1
- the block design created in vivado is different from the block design in your video HOT 7
- 自定义数据集 HOT 6
- make compile_graphical failed HOT 2
- to Lasagne from Caffe HOT 3
- 有关Python code的问题 HOT 10
- Network Structure HOT 1
- 为什么提示“TimeoutError: DMA wait timed out” HOT 2
- 请问为什么报错“TimeoutError: DMA wait timed out.”
- lenet graphical design file HOT 2
- pynq终端无法ping通网络 HOT 1
- Wrong classifications in MNIST dataset HOT 2
- Calculate the Convolution layer Parameters HOT 1
- Error rebuilding from hw/readme using tcl files. HOT 2
- src/caffe/util/io.cpp:6:10: fatal error: opencv2/core/core.hpp: No such file or directory
- fashion mnist FPGA_accuracy is very low HOT 1
- cannot make cnn block design HOT 3
- Defining batch_size for FPGA deployment HOT 1
- Use Python to run RCNN algorithm on Zedboard (Xilinx Zynq®-7000) HOT 1
- Use Python to run RCNN algorithm on Zedboard (Xilinx Zynq®-7000)
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