Comments (1)
You would need to change both the python front end and the FPGA IP cores. Regarding the python front end you need to change the network description of both the jupyter notebook and the conv_fpga.py. Regarding the backend you need to synthesise your own FPGA bitstreams
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Related Issues (20)
- [BD 5-216] VLNV <xilinx.com:hls:FC_CIF_0_1:1.0> is not supported for the current part. HOT 1
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- 自定义数据集 HOT 6
- make compile_graphical failed HOT 2
- to Lasagne from Caffe HOT 3
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- 请问为什么报错“TimeoutError: DMA wait timed out.”
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- Error rebuilding from hw/readme using tcl files. HOT 2
- src/caffe/util/io.cpp:6:10: fatal error: opencv2/core/core.hpp: No such file or directory
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- cannot make cnn block design HOT 3
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