the PYNQ resources usage about pynq-classification

[sdnuzwk]

thank you sir

[awai54st]

Hi, thank you.
As some previous issues have pointed out, this project works most stably on 2016.2. There have been reported issues with projects synthesised in 2017.1.
Can I ask which benchmark are you trying to implement? Is it lenet or cifar10, or is it your own CNN architecture?

[sdnuzwk]

@awai54st
Dear prof，
I fell excited for receiving your reply，thank you.I copy your project code about lenet and cifar10 on vivado_hls 2017.4，i do not think the version of vivado_hls is able to lead the different systhesis results，my systhesis results about lenet and cifar10 on vivado_hls 2017.4 are showed in the previous question，could you give me some advice？I am so confused because i think i follow your steps completely.
Best wishes

[sdnuzwk]

please help me sir ,i am in confused

[awai54st]

Lenet and cifar 10 are two different CNNs. Which one did you implement?

Please attach a synthesis log or report. Otherwise there’s nowhere to debug from.

[sdnuzwk]

Dear Prof,
Let me explain in detail the process of my experiment and show the comprehensive report.
I implemented cifar10 routines on vivado_hls2017.4 and vivado_hls2016.2 respectively.
1.On vivado_hls2017.4

the systhesis results about cifar10 on vivado_hls 2017.4 are showed in the picture.As you can see,the using number of LUTs are 89096,and the Estimated time is 12.59ns.

The console reports are follow:
Starting C synthesis ...
/opt/Xilinx/Vivado/2017.4/bin/vivado_hls /home/sdnuzwk/PYNQ-Classification-master/hw/script_design_flow/CIFAR_10_wrapper/CIFAR_10/solution1/csynth.tcl
INFO: [HLS 200-10] Running '/opt/Xilinx/Vivado/2017.4/bin/unwrapped/lnx64.o/vivado_hls'
INFO: [HLS 200-10] For user 'sdnuzwk' on host 'node01' (Linux_x86_64 version 3.10.0-514.el7.x86_64) on Wed May 30 10:39:23 CST 2018
INFO: [HLS 200-10] On os "CentOS Linux release 7.3.1611 (Core) "
INFO: [HLS 200-10] In directory '/home/sdnuzwk/PYNQ-Classification-master/hw/script_design_flow/CIFAR_10_wrapper'
INFO: [HLS 200-10] Opening project '/home/sdnuzwk/PYNQ-Classification-master/hw/script_design_flow/CIFAR_10_wrapper/CIFAR_10'.
INFO: [HLS 200-10] Adding design file '../hw_library/stream_convolution_slideWindow.h' to the project
INFO: [HLS 200-10] Adding design file '../hw_library/pool.h' to the project
INFO: [HLS 200-10] Adding design file '../hw_library/fully_connected.h' to the project
INFO: [HLS 200-10] Adding design file '../hw_library/fixed_point_stream_convolution.h' to the project
INFO: [HLS 200-10] Adding design file 'config.h' to the project
INFO: [HLS 200-10] Adding design file '../hw_library/axi_dma_slave.h' to the project
INFO: [HLS 200-10] Adding design file '../hw_library/axi_dma_master.h' to the project
INFO: [HLS 200-10] Adding design file 'CIFAR_10_wrapper.h' to the project
INFO: [HLS 200-10] Adding design file 'CIFAR_10_wrapper.cpp' to the project
INFO: [HLS 200-10] Opening solution '/home/sdnuzwk/PYNQ-Classification-master/hw/script_design_flow/CIFAR_10_wrapper/CIFAR_10/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-10] Setting target device to 'xc7z020clg484-1'
INFO: [HLS 200-10] Analyzing design file 'CIFAR_10_wrapper.cpp' ...
INFO: [HLS 200-10] Validating synthesis directives ...
INFO: [HLS 200-111] Finished Checking Pragmas Time (s): cpu = 00:00:48 ; elapsed = 00:00:19 . Memory (MB): peak = 449.988 ; gain = 13.379 ; free physical = 14405 ; free virtual = 124738
INFO: [HLS 200-111] Finished Linking Time (s): cpu = 00:00:49 ; elapsed = 00:00:20 . Memory (MB): peak = 449.988 ; gain = 13.379 ; free physical = 14402 ; free virtual = 124740
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms Time (s): cpu = 00:00:51 ; elapsed = 00:00:22 . Memory (MB): peak = 450.359 ; gain = 13.750 ; free physical = 14380 ; free virtual = 124727
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability Time (s): cpu = 00:00:52 ; elapsed = 00:00:23 . Memory (MB): peak = 577.984 ; gain = 141.375 ; free physical = 14365 ; free virtual = 124713
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'L3' (./../hw_library/fixed_point_stream_convolution.h:124) in function 'SMM<1u, 800u, 64u>' for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'L3' (./../hw_library/fixed_point_stream_convolution.h:124) in function 'SMM<1u, 800u, 32u>' for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'L3' (./../hw_library/fixed_point_stream_convolution.h:124) in function 'SMM<1u, 75u, 32u>' for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'Loop-1' (./../hw_library/stream_convolution_slideWindow.h:123) in function 'SCIG<5u, 3u, 32u, 32u, 32u, 2u>' for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'Loop-1' (./../hw_library/stream_convolution_slideWindow.h:123) in function 'SCIG<5u, 32u, 8u, 64u, 8u, 2u>' for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'Loop-1' (./../hw_library/stream_convolution_slideWindow.h:123) in function 'SCIG<5u, 32u, 16u, 32u, 16u, 2u>' for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'L3' (./../hw_library/fully_connected.h:124) in function 'FC<1u, 64u, 10u>' for pipelining.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'L3' (./../hw_library/fully_connected.h:124) in function 'FC<1u, 1024u, 64u>' for pipelining.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1' (./../hw_library/pool.h:124) in function 'pool<2u, 64u, 8u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-2' (./../hw_library/pool.h:130) in function 'pool<2u, 64u, 8u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1' (./../hw_library/pool.h:124) in function 'pool<2u, 32u, 32u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-2' (./../hw_library/pool.h:130) in function 'pool<2u, 32u, 32u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1' (./../hw_library/pool.h:124) in function 'pool<2u, 32u, 16u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-2' (./../hw_library/pool.h:130) in function 'pool<2u, 32u, 16u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'L4' (./../hw_library/fixed_point_stream_convolution.h:126) in function 'SMM<1u, 800u, 64u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'L4' (./../hw_library/fixed_point_stream_convolution.h:126) in function 'SMM<1u, 800u, 32u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'L4' (./../hw_library/fixed_point_stream_convolution.h:126) in function 'SMM<1u, 75u, 32u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1' (./../hw_library/stream_convolution_slideWindow.h:130) in function 'SCIG<5u, 3u, 32u, 32u, 32u, 2u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.2' (./../hw_library/stream_convolution_slideWindow.h:135) in function 'SCIG<5u, 3u, 32u, 32u, 32u, 2u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.3' (./../hw_library/stream_convolution_slideWindow.h:140) in function 'SCIG<5u, 3u, 32u, 32u, 32u, 2u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.4' (./../hw_library/stream_convolution_slideWindow.h:158) in function 'SCIG<5u, 3u, 32u, 32u, 32u, 2u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1' (./../hw_library/stream_convolution_slideWindow.h:130) in function 'SCIG<5u, 32u, 8u, 64u, 8u, 2u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.2' (./../hw_library/stream_convolution_slideWindow.h:135) in function 'SCIG<5u, 32u, 8u, 64u, 8u, 2u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.3' (./../hw_library/stream_convolution_slideWindow.h:140) in function 'SCIG<5u, 32u, 8u, 64u, 8u, 2u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.4' (./../hw_library/stream_convolution_slideWindow.h:158) in function 'SCIG<5u, 32u, 8u, 64u, 8u, 2u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.1' (./../hw_library/stream_convolution_slideWindow.h:130) in function 'SCIG<5u, 32u, 16u, 32u, 16u, 2u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.2' (./../hw_library/stream_convolution_slideWindow.h:135) in function 'SCIG<5u, 32u, 16u, 32u, 16u, 2u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.3' (./../hw_library/stream_convolution_slideWindow.h:140) in function 'SCIG<5u, 32u, 16u, 32u, 16u, 2u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'Loop-1.4' (./../hw_library/stream_convolution_slideWindow.h:158) in function 'SCIG<5u, 32u, 16u, 32u, 16u, 2u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'L4' (./../hw_library/fully_connected.h:126) in function 'FC<1u, 64u, 10u>' completely.
INFO: [XFORM 203-501] Unrolling loop 'L4' (./../hw_library/fully_connected.h:126) in function 'FC<1u, 1024u, 64u>' completely.
INFO: [XFORM 203-101] Partitioning array 'A.V.4' in dimension 2 with a block factor 25.
INFO: [XFORM 203-101] Partitioning array 'B.V.4' in dimension 2 with a block factor 25.
INFO: [XFORM 203-101] Partitioning array 'A.V.3' in dimension 2 with a block factor 25.
INFO: [XFORM 203-101] Partitioning array 'B.V.3' in dimension 2 with a block factor 25.
INFO: [XFORM 203-101] Partitioning array 'A.V.2' in dimension 2 with a block factor 25.
INFO: [XFORM 203-101] Partitioning array 'B.V.2' in dimension 2 with a block factor 25.
INFO: [XFORM 203-101] Partitioning array 'A.V.1' in dimension 2 with a block factor 16.
INFO: [XFORM 203-101] Partitioning array 'B.V.1' in dimension 2 with a block factor 16.
INFO: [XFORM 203-101] Partitioning array 'A.V' in dimension 2 with a block factor 32.
INFO: [XFORM 203-101] Partitioning array 'B.V' in dimension 2 with a block factor 32.
INFO: [XFORM 203-712] Applying dataflow to function 'cifar_10' (CIFAR_10_wrapper.cpp:4), detected/extracted 13 process function(s):
'AXI_DMA_SLAVE'
'SCIG<5u, 3u, 32u, 32u, 32u, 2u>'
'SMM<1u, 75u, 32u>'
'pool<2u, 32u, 32u>'
'SCIG<5u, 32u, 16u, 32u, 16u, 2u>'
'SMM<1u, 800u, 32u>'
'pool<2u, 32u, 16u>'
'SCIG<5u, 32u, 8u, 64u, 8u, 2u>'
'SMM<1u, 800u, 64u>'
'pool<2u, 64u, 8u>'
'FC<1u, 1024u, 64u>'
'FC<1u, 64u, 10u>'
'AXI_DMA_MASTER'.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (./../hw_library/stream_convolution_slideWindow.h:141:6) to (./../hw_library/stream_convolution_slideWindow.h:152:4) in function 'SCIG<5u, 3u, 32u, 32u, 32u, 2u>'... converting 3 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (./../hw_library/stream_convolution_slideWindow.h:141:6) to (./../hw_library/stream_convolution_slideWindow.h:152:4) in function 'SCIG<5u, 32u, 8u, 64u, 8u, 2u>'... converting 3 basic blocks.
INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (./../hw_library/stream_convolution_slideWindow.h:141:6) to (./../hw_library/stream_convolution_slideWindow.h:152:4) in function 'SCIG<5u, 32u, 16u, 32u, 16u, 2u>'... converting 3 basic blocks.
INFO: [XFORM 203-11] Balancing expressions in function 'SMM<1u, 800u, 64u>' (./../hw_library/fixed_point_stream_convolution.h:17:32)...25 expression(s) balanced.
INFO: [XFORM 203-11] Balancing expressions in function 'SMM<1u, 800u, 32u>' (./../hw_library/fixed_point_stream_convolution.h:17:32)...25 expression(s) balanced.
INFO: [XFORM 203-11] Balancing expressions in function 'SMM<1u, 75u, 32u>' (./../hw_library/fixed_point_stream_convolution.h:17:32)...25 expression(s) balanced.
INFO: [XFORM 203-11] Balancing expressions in function 'SCIG<5u, 3u, 32u, 32u, 32u, 2u>' (./../hw_library/stream_convolution_slideWindow.h:68:7)...3 expression(s) balanced.
INFO: [XFORM 203-11] Balancing expressions in function 'SCIG<5u, 32u, 16u, 32u, 16u, 2u>' (./../hw_library/stream_convolution_slideWindow.h:68:7)...3 expression(s) balanced.
INFO: [XFORM 203-11] Balancing expressions in function 'FC<1u, 64u, 10u>' (./../hw_library/fully_connected.h:17:32)...16 expression(s) balanced.
INFO: [XFORM 203-11] Balancing expressions in function 'FC<1u, 1024u, 64u>' (./../hw_library/fully_connected.h:17:32)...32 expression(s) balanced.
INFO: [HLS 200-111] Finished Pre-synthesis Time (s): cpu = 00:01:00 ; elapsed = 00:00:31 . Memory (MB): peak = 577.984 ; gain = 141.375 ; free physical = 14330 ; free virtual = 124683
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-2.1.1.1.1' (./../hw_library/pool.h:144:31) in function 'pool<2u, 64u, 8u>'.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-2.1.1.1' (./../hw_library/pool.h:142:30) in function 'pool<2u, 64u, 8u>' :

more than one sub loop.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-2.1.1' (./../hw_library/pool.h:141:29) in function 'pool<2u, 64u, 8u>'.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-2.1.2' (./../hw_library/pool.h:167:33) in function 'pool<2u, 64u, 8u>'.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-2.1' (./../hw_library/pool.h:140:28) in function 'pool<2u, 64u, 8u>' :

more than one sub loop.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-2' (./../hw_library/pool.h:139:32) in function 'pool<2u, 64u, 8u>'.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-2.1.1.1.1' (./../hw_library/pool.h:144:31) in function 'pool<2u, 32u, 32u>'.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-2.1.1.1' (./../hw_library/pool.h:142:30) in function 'pool<2u, 32u, 32u>' :

more than one sub loop.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-2.1.1' (./../hw_library/pool.h:141:29) in function 'pool<2u, 32u, 32u>'.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-2.1.2' (./../hw_library/pool.h:167:33) in function 'pool<2u, 32u, 32u>'.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-2.1' (./../hw_library/pool.h:140:28) in function 'pool<2u, 32u, 32u>' :

more than one sub loop.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-2' (./../hw_library/pool.h:139:32) in function 'pool<2u, 32u, 32u>'.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-2.1.1.1.1' (./../hw_library/pool.h:144:31) in function 'pool<2u, 32u, 16u>'.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-2.1.1.1' (./../hw_library/pool.h:142:30) in function 'pool<2u, 32u, 16u>' :

more than one sub loop.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-2.1.1' (./../hw_library/pool.h:141:29) in function 'pool<2u, 32u, 16u>'.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-2.1.2' (./../hw_library/pool.h:167:33) in function 'pool<2u, 32u, 16u>'.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-2.1' (./../hw_library/pool.h:140:28) in function 'pool<2u, 32u, 16u>' :

more than one sub loop.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-2' (./../hw_library/pool.h:139:32) in function 'pool<2u, 32u, 16u>'.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-1' (./../hw_library/fixed_point_stream_convolution.h:78:15) in function 'SMM<1u, 800u, 64u>'.
INFO: [XFORM 203-541] Flattening a loop nest 'L2' (./../hw_library/fixed_point_stream_convolution.h:122:7) in function 'SMM<1u, 800u, 64u>'.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'L1' (./../hw_library/fixed_point_stream_convolution.h:120:6) in function 'SMM<1u, 800u, 64u>' :

more than one sub loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-2' (./../hw_library/fixed_point_stream_convolution.h:96:22) in function 'SMM<1u, 800u, 64u>' :

the outer loop is not a perfect loop.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-1' (./../hw_library/fixed_point_stream_convolution.h:78:15) in function 'SMM<1u, 800u, 32u>'.
INFO: [XFORM 203-541] Flattening a loop nest 'L2' (./../hw_library/fixed_point_stream_convolution.h:122:7) in function 'SMM<1u, 800u, 32u>'.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'L1' (./../hw_library/fixed_point_stream_convolution.h:120:6) in function 'SMM<1u, 800u, 32u>' :

more than one sub loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-2' (./../hw_library/fixed_point_stream_convolution.h:96:22) in function 'SMM<1u, 800u, 32u>' :

the outer loop is not a perfect loop.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-1' (./../hw_library/fixed_point_stream_convolution.h:78:15) in function 'SMM<1u, 75u, 32u>'.
INFO: [XFORM 203-541] Flattening a loop nest 'L2' (./../hw_library/fixed_point_stream_convolution.h:122:7) in function 'SMM<1u, 75u, 32u>'.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'L1' (./../hw_library/fixed_point_stream_convolution.h:120:6) in function 'SMM<1u, 75u, 32u>' :

more than one sub loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-2' (./../hw_library/fixed_point_stream_convolution.h:96:22) in function 'SMM<1u, 75u, 32u>' :

the outer loop is not a perfect loop.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-1' (./../hw_library/fully_connected.h:78:15) in function 'FC<1u, 64u, 10u>'.
INFO: [XFORM 203-541] Flattening a loop nest 'L2' (./../hw_library/fully_connected.h:122:7) in function 'FC<1u, 64u, 10u>'.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'L1' (./../hw_library/fully_connected.h:120:6) in function 'FC<1u, 64u, 10u>' :

more than one sub loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-2' (./../hw_library/fully_connected.h:96:22) in function 'FC<1u, 64u, 10u>' :

the outer loop is not a perfect loop.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop-1' (./../hw_library/fully_connected.h:78:15) in function 'FC<1u, 1024u, 64u>'.
INFO: [XFORM 203-541] Flattening a loop nest 'L2' (./../hw_library/fully_connected.h:122:7) in function 'FC<1u, 1024u, 64u>'.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'L1' (./../hw_library/fully_connected.h:120:6) in function 'FC<1u, 1024u, 64u>' :

more than one sub loop.
WARNING: [XFORM 203-542] Cannot flatten a loop nest 'Loop-2' (./../hw_library/fully_connected.h:96:22) in function 'FC<1u, 1024u, 64u>' :

the outer loop is not a perfect loop.
WARNING: [XFORM 203-631] Renaming function 'SCIG<5u, 3u, 32u, 32u, 32u, 2u>' to 'SCIG' (./../hw_library/stream_convolution_slideWindow.h:68:7)
WARNING: [XFORM 203-631] Renaming function 'SCIG<5u, 32u, 8u, 64u, 8u, 2u>' to 'SCIG.1' (./../hw_library/stream_convolution_slideWindow.h:68:7)
WARNING: [XFORM 203-631] Renaming function 'SCIG<5u, 32u, 16u, 32u, 16u, 2u>' to 'SCIG.2' (./../hw_library/stream_convolution_slideWindow.h:68:7)
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'inputBuf.V' (./../hw_library/stream_convolution_slideWindow.h:107).
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'inputBuf.V' (./../hw_library/stream_convolution_slideWindow.h:107).
WARNING: [ANALYSIS 214-52] Found false inter dependency for variable 'inputBuf.V' (./../hw_library/stream_convolution_slideWindow.h:107).
INFO: [HLS 200-111] Finished Architecture Synthesis Time (s): cpu = 00:01:08 ; elapsed = 00:00:39 . Memory (MB): peak = 769.984 ; gain = 333.375 ; free physical = 14161 ; free virtual = 124516
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'cifar_10' ...
WARNING: [SYN 201-103] Legalizing function name 'SMM<1u, 75u, 32u>' to 'SMM_1u_75u_32u_s'.
WARNING: [SYN 201-103] Legalizing function name 'pool<2u, 32u, 32u>' to 'pool_2u_32u_32u_s'.
WARNING: [SYN 201-103] Legalizing function name 'SCIG.2' to 'SCIG_2'.
WARNING: [SYN 201-103] Legalizing function name 'SMM<1u, 800u, 32u>' to 'SMM_1u_800u_32u_s'.
WARNING: [SYN 201-103] Legalizing function name 'pool<2u, 32u, 16u>' to 'pool_2u_32u_16u_s'.
WARNING: [SYN 201-103] Legalizing function name 'SCIG.1' to 'SCIG_1'.
WARNING: [SYN 201-103] Legalizing function name 'SMM<1u, 800u, 64u>' to 'SMM_1u_800u_64u_s'.
WARNING: [SYN 201-103] Legalizing function name 'pool<2u, 64u, 8u>' to 'pool_2u_64u_8u_s'.
WARNING: [SYN 201-103] Legalizing function name 'FC<1u, 1024u, 64u>' to 'FC_1u_1024u_64u_s'.
WARNING: [SYN 201-103] Legalizing function name 'FC<1u, 64u, 10u>' to 'FC_1u_64u_10u_s'.
WARNING: [SYN 201-303] Cannot apply functional unit assignment of 'Mul_LUT' (./../hw_library/stream_convolution_slideWindow.h:105): '' does not exist or is optimized away.
WARNING: [SYN 201-303] Cannot apply functional unit assignment of 'Mul_LUT' (./../hw_library/stream_convolution_slideWindow.h:105): '' does not exist or is optimized away.
WARNING: [SYN 201-303] Cannot apply functional unit assignment of 'Mul_LUT' (./../hw_library/stream_convolution_slideWindow.h:105): '' does not exist or is optimized away.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'AXI_DMA_SLAVE'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
WARNING: [SCHED 204-21] Estimated delay (12.6ns) of 'mul' operation ('KER_size_0', ./../hw_library/axi_dma_slave.h:56) exceeds the target cycle time (target cycle time: 10ns, clock uncertainty: 1.25ns, effective cycle time: 8.75ns).
INFO: [SCHED 204-61] Pipelining loop 'Loop 2'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
WARNING: [SCHED 204-21] Estimated clock period (12.592ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'mul' operation ('KER_size_0', ./../hw_library/axi_dma_slave.h:56) (12.6 ns)
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 39.46 seconds; current allocated memory: 281.775 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.14 seconds; current allocated memory: 282.066 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'SCIG'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
WARNING: [SCHED 204-21] Estimated delay (12.6ns) of 'mul' operation ('KER_size_0', ./../hw_library/stream_convolution_slideWindow.h:183) exceeds the target cycle time (target cycle time: 10ns, clock uncertainty: 1.25ns, effective cycle time: 8.75ns).
INFO: [SCHED 204-61] Pipelining loop 'Loop 2'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1)
between 'load' operation ('inElem_V_load', ./../hw_library/stream_convolution_slideWindow.h:141) on array 'inElem.V', ./../hw_library/stream_convolution_slideWindow.h:127 and 'store' operation (./../hw_library/stream_convolution_slideWindow.h:137) of variable 'tmp_239', ./../hw_library/stream_convolution_slideWindow.h:137 on array 'inElem.V', ./../hw_library/stream_convolution_slideWindow.h:127.
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1)
between fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136) and fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136).
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 3, Depth = 9.
WARNING: [SCHED 204-21] Estimated clock period (12.592ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'mul' operation ('KER_size_0', ./../hw_library/stream_convolution_slideWindow.h:183) (12.6 ns)
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.71 seconds; current allocated memory: 282.926 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
WARNING: [BIND 205-102] The specified resource core for memory 'inElem_V' will be ignored if a simpler one can be used.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.22 seconds; current allocated memory: 283.641 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'SMM_1u_75u_32u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
WARNING: [SCHED 204-21] Estimated delay (12.6ns) of 'mul' operation ('KER_size_0', ./../hw_library/fixed_point_stream_convolution.h:143) exceeds the target cycle time (target cycle time: 10ns, clock uncertainty: 1.25ns, effective cycle time: 8.75ns).
INFO: [SCHED 204-61] Pipelining loop 'Loop 3'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'L1.1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'L2_L3'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 8.
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 12.
WARNING: [SCHED 204-21] Estimated clock period (12.592ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'mul' operation ('KER_size_0', ./../hw_library/fixed_point_stream_convolution.h:143) (12.6 ns)
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 1.17 seconds; current allocated memory: 286.852 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.81 seconds; current allocated memory: 289.241 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'pool_2u_32u_32u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
WARNING: [SCHED 204-21] Estimated delay (12.6ns) of 'mul' operation ('KER_size_0', ./../hw_library/pool.h:188) exceeds the target cycle time (target cycle time: 10ns, clock uncertainty: 1.25ns, effective cycle time: 8.75ns).
INFO: [SCHED 204-61] Pipelining loop 'Loop 3'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'Loop 2.1.1'.
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1)
between 'store' operation (./../hw_library/pool.h:148) of variable 'acc_load_2_valIn_V', ./../hw_library/pool.h:148 on array 'acc', ./../hw_library/pool.h:121 and 'load' operation ('acc_load_2', ./../hw_library/pool.h:148) on array 'acc', ./../hw_library/pool.h:121.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 3.
INFO: [SCHED 204-61] Pipelining loop 'Loop 2.1.2'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [SCHED 204-61] Pipelining loop 'Loop 2.2'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
WARNING: [SCHED 204-21] Estimated clock period (12.592ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'mul' operation ('KER_size_0', ./../hw_library/pool.h:188) (12.6 ns)
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 1.25 seconds; current allocated memory: 290.515 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
WARNING: [BIND 205-102] The specified resource core for memory 'buf' will be ignored if a simpler one can be used.
WARNING: [BIND 205-102] The specified resource core for memory 'acc' will be ignored if a simpler one can be used.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.41 seconds; current allocated memory: 291.528 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'SCIG_2'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
WARNING: [SCHED 204-21] Estimated delay (12.6ns) of 'mul' operation ('KER_size_0', ./../hw_library/stream_convolution_slideWindow.h:183) exceeds the target cycle time (target cycle time: 10ns, clock uncertainty: 1.25ns, effective cycle time: 8.75ns).
INFO: [SCHED 204-61] Pipelining loop 'Loop 2'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1)
between 'load' operation ('inElem_V_load', ./../hw_library/stream_convolution_slideWindow.h:141) on array 'inElem.V', ./../hw_library/stream_convolution_slideWindow.h:127 and 'store' operation (./../hw_library/stream_convolution_slideWindow.h:137) of variable 'tmp_152', ./../hw_library/stream_convolution_slideWindow.h:137 on array 'inElem.V', ./../hw_library/stream_convolution_slideWindow.h:127.
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1)
between fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136) and fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136).
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1)
between fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136) and fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136).
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1)
between fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136) and fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136).
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1)
between fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136) and fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136).
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1)
between fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136) and fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136).
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1)
between fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136) and fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136).
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 32, Depth = 37.
WARNING: [SCHED 204-21] Estimated clock period (12.592ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'mul' operation ('KER_size_0', ./../hw_library/stream_convolution_slideWindow.h:183) (12.6 ns)
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 3.63 seconds; current allocated memory: 294.103 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
WARNING: [BIND 205-102] The specified resource core for memory 'inElem_V' will be ignored if a simpler one can be used.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.79 seconds; current allocated memory: 296.083 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'SMM_1u_800u_32u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
WARNING: [SCHED 204-21] Estimated delay (12.6ns) of 'mul' operation ('KER_size_0', ./../hw_library/fixed_point_stream_convolution.h:143) exceeds the target cycle time (target cycle time: 10ns, clock uncertainty: 1.25ns, effective cycle time: 8.75ns).
INFO: [SCHED 204-61] Pipelining loop 'Loop 3'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'L1.1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'L2_L3'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 8.
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
WARNING: [SCHED 204-21] Estimated clock period (12.592ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'mul' operation ('KER_size_0', ./../hw_library/fixed_point_stream_convolution.h:143) (12.6 ns)
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 1.61 seconds; current allocated memory: 299.349 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.74 seconds; current allocated memory: 301.467 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'pool_2u_32u_16u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
WARNING: [SCHED 204-21] Estimated delay (12.6ns) of 'mul' operation ('KER_size_0', ./../hw_library/pool.h:188) exceeds the target cycle time (target cycle time: 10ns, clock uncertainty: 1.25ns, effective cycle time: 8.75ns).
INFO: [SCHED 204-61] Pipelining loop 'Loop 3'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'Loop 2.1.1'.
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1)
between 'store' operation (./../hw_library/pool.h:149) of variable 'tmp_40', ./../hw_library/pool.h:149 on array 'acc', ./../hw_library/pool.h:121 and 'load' operation ('i_op', ./../hw_library/pool.h:149) on array 'acc', ./../hw_library/pool.h:121.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'Loop 2.1.2'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'Loop 2.2'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
WARNING: [SCHED 204-21] Estimated clock period (12.592ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'mul' operation ('KER_size_0', ./../hw_library/pool.h:188) (12.6 ns)
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 1.16 seconds; current allocated memory: 302.640 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
WARNING: [BIND 205-102] The specified resource core for memory 'buf' will be ignored if a simpler one can be used.
WARNING: [BIND 205-102] The specified resource core for memory 'acc' will be ignored if a simpler one can be used.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.35 seconds; current allocated memory: 303.566 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'SCIG_1'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
WARNING: [SCHED 204-21] Estimated delay (12.6ns) of 'mul' operation ('KER_size_0', ./../hw_library/stream_convolution_slideWindow.h:183) exceeds the target cycle time (target cycle time: 10ns, clock uncertainty: 1.25ns, effective cycle time: 8.75ns).
INFO: [SCHED 204-61] Pipelining loop 'Loop 2'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1)
between 'load' operation ('inElem_V_load', ./../hw_library/stream_convolution_slideWindow.h:141) on array 'inElem.V', ./../hw_library/stream_convolution_slideWindow.h:127 and 'store' operation (./../hw_library/stream_convolution_slideWindow.h:137) of variable 'tmp_196', ./../hw_library/stream_convolution_slideWindow.h:137 on array 'inElem.V', ./../hw_library/stream_convolution_slideWindow.h:127.
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 2, distance = 1, offset = 1)
between fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136) and fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136).
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 3, distance = 1, offset = 1)
between fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136) and fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136).
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 4, distance = 1, offset = 1)
between fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136) and fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136).
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 19, distance = 1, offset = 1)
between fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136) and fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136).
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 27, distance = 1, offset = 1)
between fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136) and fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136).
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 31, distance = 1, offset = 1)
between fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136) and fifo read on port 'in_V_V' (./../hw_library/stream_convolution_slideWindow.h:136).
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 32, Depth = 37.
WARNING: [SCHED 204-21] Estimated clock period (12.592ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'mul' operation ('KER_size_0', ./../hw_library/stream_convolution_slideWindow.h:183) (12.6 ns)
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 3.31 seconds; current allocated memory: 306.076 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
WARNING: [BIND 205-102] The specified resource core for memory 'inElem_V' will be ignored if a simpler one can be used.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.81 seconds; current allocated memory: 308.058 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'SMM_1u_800u_64u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
WARNING: [SCHED 204-21] Estimated delay (12.6ns) of 'mul' operation ('KER_size_0', ./../hw_library/fixed_point_stream_convolution.h:143) exceeds the target cycle time (target cycle time: 10ns, clock uncertainty: 1.25ns, effective cycle time: 8.75ns).
INFO: [SCHED 204-61] Pipelining loop 'Loop 3'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'L1.1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'L2_L3'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 8.
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
WARNING: [SCHED 204-21] Estimated clock period (12.592ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'mul' operation ('KER_size_0', ./../hw_library/fixed_point_stream_convolution.h:143) (12.6 ns)
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 1.81 seconds; current allocated memory: 311.287 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.73 seconds; current allocated memory: 313.444 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'pool_2u_64u_8u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
WARNING: [SCHED 204-21] Estimated delay (12.6ns) of 'mul' operation ('KER_size_0', ./../hw_library/pool.h:188) exceeds the target cycle time (target cycle time: 10ns, clock uncertainty: 1.25ns, effective cycle time: 8.75ns).
INFO: [SCHED 204-61] Pipelining loop 'Loop 3'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'Loop 2.1.1'.
WARNING: [SCHED 204-68] Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1)
between 'store' operation (./../hw_library/pool.h:149) of variable 'tmp_16', ./../hw_library/pool.h:149 on array 'acc', ./../hw_library/pool.h:121 and 'load' operation ('i_op', ./../hw_library/pool.h:149) on array 'acc', ./../hw_library/pool.h:121.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 2, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'Loop 2.1.2'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'Loop 2.2'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
WARNING: [SCHED 204-21] Estimated clock period (12.592ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'mul' operation ('KER_size_0', ./../hw_library/pool.h:188) (12.6 ns)
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 1.23 seconds; current allocated memory: 314.763 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
WARNING: [BIND 205-102] The specified resource core for memory 'buf' will be ignored if a simpler one can be used.
WARNING: [BIND 205-102] The specified resource core for memory 'acc' will be ignored if a simpler one can be used.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.45 seconds; current allocated memory: 315.849 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'FC_1u_1024u_64u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
WARNING: [SCHED 204-21] Estimated delay (12.6ns) of 'mul' operation ('KER_size_0', ./../hw_library/fully_connected.h:143) exceeds the target cycle time (target cycle time: 10ns, clock uncertainty: 1.25ns, effective cycle time: 8.75ns).
INFO: [SCHED 204-61] Pipelining loop 'Loop 3'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'L1.1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'L2_L3'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 8.
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
WARNING: [SCHED 204-21] Estimated clock period (12.592ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'mul' operation ('KER_size_0', ./../hw_library/fully_connected.h:143) (12.6 ns)
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 1.66 seconds; current allocated memory: 319.719 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.89 seconds; current allocated memory: 322.367 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'FC_1u_64u_10u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
WARNING: [SCHED 204-21] Estimated delay (12.6ns) of 'mul' operation ('KER_size_0', ./../hw_library/fully_connected.h:143) exceeds the target cycle time (target cycle time: 10ns, clock uncertainty: 1.25ns, effective cycle time: 8.75ns).
INFO: [SCHED 204-61] Pipelining loop 'Loop 3'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'L1.1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
INFO: [SCHED 204-61] Pipelining loop 'L2_L3'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 8.
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 2.
WARNING: [SCHED 204-21] Estimated clock period (12.592ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'mul' operation ('KER_size_0', ./../hw_library/fully_connected.h:143) (12.6 ns)
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 1.55 seconds; current allocated memory: 324.701 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.54 seconds; current allocated memory: 326.359 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'AXI_DMA_MASTER'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
WARNING: [SCHED 204-21] Estimated delay (12.6ns) of 'mul' operation ('KER_size_0', ./../hw_library/axi_dma_master.h:67) exceeds the target cycle time (target cycle time: 10ns, clock uncertainty: 1.25ns, effective cycle time: 8.75ns).
INFO: [SCHED 204-61] Pipelining loop 'Loop 2'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
INFO: [SCHED 204-61] Pipelining loop 'Loop 1'.
INFO: [SCHED 204-61] Pipelining result : Target II = 1, Final II = 1, Depth = 3.
WARNING: [SCHED 204-21] Estimated clock period (12.592ns) exceeds the target (target clock period: 10ns, clock uncertainty: 1.25ns, effective delay budget: 8.75ns).
WARNING: [SCHED 204-21] The critical path consists of the following:
'mul' operation ('KER_size_0', ./../hw_library/axi_dma_master.h:67) (12.6 ns)
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.72 seconds; current allocated memory: 326.740 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 0.11 seconds; current allocated memory: 327.043 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'cifar_10'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Elapsed time: 0.13 seconds; current allocated memory: 327.357 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Elapsed time: 2.98 seconds; current allocated memory: 329.609 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'AXI_DMA_SLAVE'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SYN 201-210] Renamed object name 'cifar_10_mul_32s_32s_32_1_1' to 'cifar_10_mul_32s_bkb' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_bkb': 6 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'AXI_DMA_SLAVE'.
INFO: [HLS 200-111] Elapsed time: 1.45 seconds; current allocated memory: 330.845 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'SCIG'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SYN 201-210] Renamed object name 'cifar_10_mul_32s_16ns_32_1_1' to 'cifar_10_mul_32s_cud' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_bkb': 3 instance(s).
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_cud': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'SCIG'.
INFO: [HLS 200-111] Elapsed time: 0.46 seconds; current allocated memory: 333.077 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'SMM_1u_75u_32u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Register 'B_COL_2' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'B_ROW_2' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'OFMDim_current_2' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'A_ROW_2' is power-on initialization.
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_0' to 'SMM_1u_75u_32u_s_dEe' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_0' to 'SMM_1u_75u_32u_s_eOg' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_1' to 'SMM_1u_75u_32u_s_fYi' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_1' to 'SMM_1u_75u_32u_s_g8j' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_2' to 'SMM_1u_75u_32u_s_hbi' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_2' to 'SMM_1u_75u_32u_s_ibs' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_3' to 'SMM_1u_75u_32u_s_jbC' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_3' to 'SMM_1u_75u_32u_s_kbM' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_4' to 'SMM_1u_75u_32u_s_lbW' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_4' to 'SMM_1u_75u_32u_s_mb6' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_5' to 'SMM_1u_75u_32u_s_ncg' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_5' to 'SMM_1u_75u_32u_s_ocq' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_6' to 'SMM_1u_75u_32u_s_pcA' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_6' to 'SMM_1u_75u_32u_s_qcK' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_7' to 'SMM_1u_75u_32u_s_rcU' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_7' to 'SMM_1u_75u_32u_s_sc4' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_8' to 'SMM_1u_75u_32u_s_tde' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_8' to 'SMM_1u_75u_32u_s_udo' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_9' to 'SMM_1u_75u_32u_s_vdy' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_9' to 'SMM_1u_75u_32u_s_wdI' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_10' to 'SMM_1u_75u_32u_s_xdS' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_10' to 'SMM_1u_75u_32u_s_yd2' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_11' to 'SMM_1u_75u_32u_s_zec' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_11' to 'SMM_1u_75u_32u_s_Aem' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_12' to 'SMM_1u_75u_32u_s_Bew' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_12' to 'SMM_1u_75u_32u_s_CeG' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_13' to 'SMM_1u_75u_32u_s_DeQ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_13' to 'SMM_1u_75u_32u_s_Ee0' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_14' to 'SMM_1u_75u_32u_s_Ffa' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_14' to 'SMM_1u_75u_32u_s_Gfk' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_15' to 'SMM_1u_75u_32u_s_Hfu' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_15' to 'SMM_1u_75u_32u_s_IfE' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_16' to 'SMM_1u_75u_32u_s_JfO' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_16' to 'SMM_1u_75u_32u_s_KfY' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_17' to 'SMM_1u_75u_32u_s_Lf8' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_17' to 'SMM_1u_75u_32u_s_Mgi' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_18' to 'SMM_1u_75u_32u_s_Ngs' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_18' to 'SMM_1u_75u_32u_s_OgC' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_19' to 'SMM_1u_75u_32u_s_PgM' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_19' to 'SMM_1u_75u_32u_s_QgW' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_20' to 'SMM_1u_75u_32u_s_Rg6' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_20' to 'SMM_1u_75u_32u_s_Shg' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_21' to 'SMM_1u_75u_32u_s_Thq' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_21' to 'SMM_1u_75u_32u_s_UhA' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_22' to 'SMM_1u_75u_32u_s_VhK' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_22' to 'SMM_1u_75u_32u_s_WhU' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_23' to 'SMM_1u_75u_32u_s_Xh4' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_23' to 'SMM_1u_75u_32u_s_Yie' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_A_V_2_24' to 'SMM_1u_75u_32u_s_Zio' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_75u_32u_s_B_V_2_24' to 'SMM_1u_75u_32u_s_0iy' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'cifar_10_urem_7ns_3ns_7_11_1' to 'cifar_10_urem_7ns1iI' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'cifar_10_mul_mul_16s_16s_32_1_1' to 'cifar_10_mul_mul_2iS' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'cifar_10_mac_muladd_16s_16s_32s_32_1_1' to 'cifar_10_mac_mula3i2' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mac_mula3i2': 16 instance(s).
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_bkb': 3 instance(s).
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_mul_2iS': 9 instance(s).
INFO: [RTGEN 206-100] Generating core module 'cifar_10_urem_7ns1iI': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'SMM_1u_75u_32u_s'.
INFO: [HLS 200-111] Elapsed time: 1.72 seconds; current allocated memory: 340.381 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'pool_2u_32u_32u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Register 'IFMCH_curr_1' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'IFMDim_curr_1' is power-on initialization.
INFO: [SYN 201-210] Renamed object name 'pool_2u_32u_32u_s_buf' to 'pool_2u_32u_32u_s4jc' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'pool_2u_32u_32u_s_acc' to 'pool_2u_32u_32u_s5jm' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_bkb': 3 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'pool_2u_32u_32u_s'.
INFO: [HLS 200-111] Elapsed time: 2.35 seconds; current allocated memory: 351.915 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'SCIG_2'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SYN 201-210] Renamed object name 'cifar_10_mul_32s_14ns_32_1_1' to 'cifar_10_mul_32s_6jw' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_6jw': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_bkb': 3 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'SCIG_2'.
INFO: [HLS 200-111] Elapsed time: 1.7 seconds; current allocated memory: 360.394 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'SMM_1u_800u_32u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Register 'B_COL_1' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'B_ROW_1' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'OFMDim_current_1' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'A_ROW_1' is power-on initialization.
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_0' to 'SMM_1u_800u_32u_s7jG' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_0' to 'SMM_1u_800u_32u_s8jQ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_1' to 'SMM_1u_800u_32u_s9j0' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_1' to 'SMM_1u_800u_32u_sbak' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_2' to 'SMM_1u_800u_32u_sbbk' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_2' to 'SMM_1u_800u_32u_sbck' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_3' to 'SMM_1u_800u_32u_sbdk' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_3' to 'SMM_1u_800u_32u_sbek' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_4' to 'SMM_1u_800u_32u_sbfk' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_4' to 'SMM_1u_800u_32u_sbgk' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_5' to 'SMM_1u_800u_32u_sbhl' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_5' to 'SMM_1u_800u_32u_sbil' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_6' to 'SMM_1u_800u_32u_sbjl' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_6' to 'SMM_1u_800u_32u_sbkl' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_7' to 'SMM_1u_800u_32u_sbll' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_7' to 'SMM_1u_800u_32u_sbml' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_8' to 'SMM_1u_800u_32u_sbnm' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_8' to 'SMM_1u_800u_32u_sbom' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_9' to 'SMM_1u_800u_32u_sbpm' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_9' to 'SMM_1u_800u_32u_sbqm' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_10' to 'SMM_1u_800u_32u_sbrm' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_10' to 'SMM_1u_800u_32u_sbsm' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_11' to 'SMM_1u_800u_32u_sbtn' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_11' to 'SMM_1u_800u_32u_sbun' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_12' to 'SMM_1u_800u_32u_sbvn' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_12' to 'SMM_1u_800u_32u_sbwn' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_13' to 'SMM_1u_800u_32u_sbxn' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_13' to 'SMM_1u_800u_32u_sbyn' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_14' to 'SMM_1u_800u_32u_sbzo' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_14' to 'SMM_1u_800u_32u_sbAo' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_15' to 'SMM_1u_800u_32u_sbBo' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_15' to 'SMM_1u_800u_32u_sbCo' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_16' to 'SMM_1u_800u_32u_sbDo' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_16' to 'SMM_1u_800u_32u_sbEo' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_17' to 'SMM_1u_800u_32u_sbFp' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_17' to 'SMM_1u_800u_32u_sbGp' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_18' to 'SMM_1u_800u_32u_sbHp' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_18' to 'SMM_1u_800u_32u_sbIp' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_19' to 'SMM_1u_800u_32u_sbJp' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_19' to 'SMM_1u_800u_32u_sbKp' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_20' to 'SMM_1u_800u_32u_sbLp' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_20' to 'SMM_1u_800u_32u_sbMq' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_21' to 'SMM_1u_800u_32u_sbNq' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_21' to 'SMM_1u_800u_32u_sbOq' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_22' to 'SMM_1u_800u_32u_sbPq' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_22' to 'SMM_1u_800u_32u_sbQq' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_23' to 'SMM_1u_800u_32u_sbRq' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_23' to 'SMM_1u_800u_32u_sbSr' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_A_V_3_24' to 'SMM_1u_800u_32u_sbTr' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_32u_s_B_V_3_24' to 'SMM_1u_800u_32u_sbUr' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mac_mula3i2': 16 instance(s).
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_bkb': 3 instance(s).
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_mul_2iS': 9 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'SMM_1u_800u_32u_s'.
INFO: [HLS 200-111] Elapsed time: 2.87 seconds; current allocated memory: 372.909 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'pool_2u_32u_16u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Register 'IFMCH_curr_2' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'IFMDim_curr_2' is power-on initialization.
INFO: [SYN 201-210] Renamed object name 'pool_2u_32u_16u_s_buf' to 'pool_2u_32u_16u_sbVr' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'pool_2u_32u_16u_s_acc' to 'pool_2u_32u_16u_sbWr' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_bkb': 3 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'pool_2u_32u_16u_s'.
INFO: [HLS 200-111] Elapsed time: 2.07 seconds; current allocated memory: 383.822 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'SCIG_1'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SYN 201-210] Renamed object name 'cifar_10_mul_32s_12ns_32_1_1' to 'cifar_10_mul_32s_bXr' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_bXr': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_bkb': 3 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'SCIG_1'.
INFO: [HLS 200-111] Elapsed time: 1.71 seconds; current allocated memory: 391.707 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'SMM_1u_800u_64u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Register 'B_COL' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'B_ROW' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'OFMDim_current' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'A_ROW' is power-on initialization.
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_0' to 'SMM_1u_800u_64u_sbYs' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_0' to 'SMM_1u_800u_64u_sbZs' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_1' to 'SMM_1u_800u_64u_sb0s' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_1' to 'SMM_1u_800u_64u_sb1s' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_2' to 'SMM_1u_800u_64u_sb2s' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_2' to 'SMM_1u_800u_64u_sb3s' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_3' to 'SMM_1u_800u_64u_sb4t' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_3' to 'SMM_1u_800u_64u_sb5t' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_4' to 'SMM_1u_800u_64u_sb6t' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_4' to 'SMM_1u_800u_64u_sb7t' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_5' to 'SMM_1u_800u_64u_sb8t' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_5' to 'SMM_1u_800u_64u_sb9t' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_6' to 'SMM_1u_800u_64u_scau' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_6' to 'SMM_1u_800u_64u_scbu' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_7' to 'SMM_1u_800u_64u_sccu' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_7' to 'SMM_1u_800u_64u_scdu' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_8' to 'SMM_1u_800u_64u_sceu' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_8' to 'SMM_1u_800u_64u_scfu' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_9' to 'SMM_1u_800u_64u_scgu' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_9' to 'SMM_1u_800u_64u_schv' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_10' to 'SMM_1u_800u_64u_sciv' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_10' to 'SMM_1u_800u_64u_scjv' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_11' to 'SMM_1u_800u_64u_sckv' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_11' to 'SMM_1u_800u_64u_sclv' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_12' to 'SMM_1u_800u_64u_scmv' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_12' to 'SMM_1u_800u_64u_scnw' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_13' to 'SMM_1u_800u_64u_scow' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_13' to 'SMM_1u_800u_64u_scpw' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_14' to 'SMM_1u_800u_64u_scqw' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_14' to 'SMM_1u_800u_64u_scrw' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_15' to 'SMM_1u_800u_64u_scsw' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_15' to 'SMM_1u_800u_64u_sctx' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_16' to 'SMM_1u_800u_64u_scux' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_16' to 'SMM_1u_800u_64u_scvx' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_17' to 'SMM_1u_800u_64u_scwx' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_17' to 'SMM_1u_800u_64u_scxx' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_18' to 'SMM_1u_800u_64u_scyx' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_18' to 'SMM_1u_800u_64u_sczy' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_19' to 'SMM_1u_800u_64u_scAy' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_19' to 'SMM_1u_800u_64u_scBy' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_20' to 'SMM_1u_800u_64u_scCy' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_20' to 'SMM_1u_800u_64u_scDy' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_21' to 'SMM_1u_800u_64u_scEy' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_21' to 'SMM_1u_800u_64u_scFz' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_22' to 'SMM_1u_800u_64u_scGz' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_22' to 'SMM_1u_800u_64u_scHz' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_23' to 'SMM_1u_800u_64u_scIz' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_23' to 'SMM_1u_800u_64u_scJz' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_A_V_4_24' to 'SMM_1u_800u_64u_scKz' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'SMM_1u_800u_64u_s_B_V_4_24' to 'SMM_1u_800u_64u_scLz' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mac_mula3i2': 16 instance(s).
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_bkb': 3 instance(s).
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_mul_2iS': 9 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'SMM_1u_800u_64u_s'.
INFO: [HLS 200-111] Elapsed time: 2.84 seconds; current allocated memory: 404.274 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'pool_2u_64u_8u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Register 'IFMCH_curr' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'IFMDim_curr' is power-on initialization.
INFO: [SYN 201-210] Renamed object name 'pool_2u_64u_8u_s_buf' to 'pool_2u_64u_8u_s_cMA' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'pool_2u_64u_8u_s_acc' to 'pool_2u_64u_8u_s_cNA' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_bkb': 3 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'pool_2u_64u_8u_s'.
INFO: [HLS 200-111] Elapsed time: 2.26 seconds; current allocated memory: 415.691 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'FC_1u_1024u_64u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Register 'B_COL_4' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'B_ROW_4' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'OFMDim_current_4' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'A_ROW_4' is power-on initialization.
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_0' to 'FC_1u_1024u_64u_scOA' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_0' to 'FC_1u_1024u_64u_scPA' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_1123' to 'FC_1u_1024u_64u_scQA' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_1127' to 'FC_1u_1024u_64u_scRA' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_2124' to 'FC_1u_1024u_64u_scSB' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_2128' to 'FC_1u_1024u_64u_scTB' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_3125' to 'FC_1u_1024u_64u_scUB' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_3129' to 'FC_1u_1024u_64u_scVB' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_4126' to 'FC_1u_1024u_64u_scWB' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_4130' to 'FC_1u_1024u_64u_scXB' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_5' to 'FC_1u_1024u_64u_scYC' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_5' to 'FC_1u_1024u_64u_scZC' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_6' to 'FC_1u_1024u_64u_sc0C' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_6' to 'FC_1u_1024u_64u_sc1C' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_7' to 'FC_1u_1024u_64u_sc2C' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_7' to 'FC_1u_1024u_64u_sc3C' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_8' to 'FC_1u_1024u_64u_sc4D' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_8' to 'FC_1u_1024u_64u_sc5D' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_9' to 'FC_1u_1024u_64u_sc6D' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_9' to 'FC_1u_1024u_64u_sc7D' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_10' to 'FC_1u_1024u_64u_sc8D' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_10' to 'FC_1u_1024u_64u_sc9D' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_11' to 'FC_1u_1024u_64u_sdaE' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_11' to 'FC_1u_1024u_64u_sdbE' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_12' to 'FC_1u_1024u_64u_sdcE' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_12' to 'FC_1u_1024u_64u_sddE' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_13' to 'FC_1u_1024u_64u_sdeE' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_13' to 'FC_1u_1024u_64u_sdfE' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_14' to 'FC_1u_1024u_64u_sdgE' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_14' to 'FC_1u_1024u_64u_sdhF' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_15' to 'FC_1u_1024u_64u_sdiF' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_15' to 'FC_1u_1024u_64u_sdjF' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_16' to 'FC_1u_1024u_64u_sdkF' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_16' to 'FC_1u_1024u_64u_sdlF' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_17' to 'FC_1u_1024u_64u_sdmF' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_17' to 'FC_1u_1024u_64u_sdnG' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_18' to 'FC_1u_1024u_64u_sdoG' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_18' to 'FC_1u_1024u_64u_sdpG' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_19' to 'FC_1u_1024u_64u_sdqG' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_19' to 'FC_1u_1024u_64u_sdrG' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_20' to 'FC_1u_1024u_64u_sdsG' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_20' to 'FC_1u_1024u_64u_sdtH' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_21' to 'FC_1u_1024u_64u_sduH' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_21' to 'FC_1u_1024u_64u_sdvH' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_22' to 'FC_1u_1024u_64u_sdwH' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_22' to 'FC_1u_1024u_64u_sdxH' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_23' to 'FC_1u_1024u_64u_sdyH' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_23' to 'FC_1u_1024u_64u_sdzI' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_24' to 'FC_1u_1024u_64u_sdAI' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_24' to 'FC_1u_1024u_64u_sdBI' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_25' to 'FC_1u_1024u_64u_sdCI' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_25' to 'FC_1u_1024u_64u_sdDI' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_26' to 'FC_1u_1024u_64u_sdEI' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_26' to 'FC_1u_1024u_64u_sdFJ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_27' to 'FC_1u_1024u_64u_sdGJ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_27' to 'FC_1u_1024u_64u_sdHJ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_28' to 'FC_1u_1024u_64u_sdIJ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_28' to 'FC_1u_1024u_64u_sdJJ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_29' to 'FC_1u_1024u_64u_sdKJ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_29' to 'FC_1u_1024u_64u_sdLJ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_30' to 'FC_1u_1024u_64u_sdMK' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_30' to 'FC_1u_1024u_64u_sdNK' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_A_V_31' to 'FC_1u_1024u_64u_sdOK' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_1024u_64u_s_B_V_31' to 'FC_1u_1024u_64u_sdPK' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mac_mula3i2': 16 instance(s).
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_bkb': 3 instance(s).
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_mul_2iS': 16 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'FC_1u_1024u_64u_s'.
INFO: [HLS 200-111] Elapsed time: 2.83 seconds; current allocated memory: 425.057 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'FC_1u_64u_10u_s'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Register 'B_COL_3' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'B_ROW_3' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'OFMDim_current_3' is power-on initialization.
WARNING: [RTGEN 206-101] Register 'A_ROW_3' is power-on initialization.
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_0' to 'FC_1u_64u_10u_s_AdQK' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_0' to 'FC_1u_64u_10u_s_BdRK' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_1' to 'FC_1u_64u_10u_s_AdSL' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_1' to 'FC_1u_64u_10u_s_BdTL' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_2' to 'FC_1u_64u_10u_s_AdUL' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_2' to 'FC_1u_64u_10u_s_BdVL' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_3' to 'FC_1u_64u_10u_s_AdWL' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_3' to 'FC_1u_64u_10u_s_BdXL' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_4' to 'FC_1u_64u_10u_s_AdYM' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_4' to 'FC_1u_64u_10u_s_BdZM' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_5' to 'FC_1u_64u_10u_s_Ad0M' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_5' to 'FC_1u_64u_10u_s_Bd1M' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_6' to 'FC_1u_64u_10u_s_Ad2M' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_6' to 'FC_1u_64u_10u_s_Bd3M' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_7' to 'FC_1u_64u_10u_s_Ad4N' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_7' to 'FC_1u_64u_10u_s_Bd5N' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_8' to 'FC_1u_64u_10u_s_Ad6N' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_8' to 'FC_1u_64u_10u_s_Bd7N' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_9' to 'FC_1u_64u_10u_s_Ad8N' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_9' to 'FC_1u_64u_10u_s_Bd9N' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_10' to 'FC_1u_64u_10u_s_AeaO' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_10' to 'FC_1u_64u_10u_s_BebO' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_11' to 'FC_1u_64u_10u_s_AecO' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_11' to 'FC_1u_64u_10u_s_BedO' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_12' to 'FC_1u_64u_10u_s_AeeO' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_12' to 'FC_1u_64u_10u_s_BefO' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_13' to 'FC_1u_64u_10u_s_AegO' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_13' to 'FC_1u_64u_10u_s_BehP' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_14' to 'FC_1u_64u_10u_s_AeiP' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_14' to 'FC_1u_64u_10u_s_BejP' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_A_V_1_15' to 'FC_1u_64u_10u_s_AekP' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'FC_1u_64u_10u_s_B_V_1_15' to 'FC_1u_64u_10u_s_BelP' due to the length limit 20
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mac_mula3i2': 8 instance(s).
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_bkb': 3 instance(s).
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_mul_2iS': 8 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'FC_1u_64u_10u_s'.
INFO: [HLS 200-111] Elapsed time: 3.13 seconds; current allocated memory: 439.520 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'AXI_DMA_MASTER'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-100] Generating core module 'cifar_10_mul_32s_bkb': 6 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'AXI_DMA_MASTER'.
INFO: [HLS 200-111] Elapsed time: 1.37 seconds; current allocated memory: 447.220 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'cifar_10'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-500] Setting interface mode on port 'cifar_10/in_stream_V_data_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'cifar_10/in_stream_V_last' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'cifar_10/out_stream_V_data_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'cifar_10/out_stream_V_last' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on function 'cifar_10' to 'ap_ctrl_none'.
INFO: [SYN 201-210] Renamed object name 'start_for_SMM_1u_75u_32u_U0' to 'start_for_SMM_1u_emP' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'start_for_pool_2u_32u_32u_U0' to 'start_for_pool_2uenQ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'start_for_SMM_1u_800u_32u_U0' to 'start_for_SMM_1u_eoQ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'start_for_pool_2u_32u_16u_U0' to 'start_for_pool_2uepQ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'start_for_SMM_1u_800u_64u_U0' to 'start_for_SMM_1u_eqQ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'start_for_pool_2u_64u_8u_U0' to 'start_for_pool_2uerQ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'start_for_FC_1u_1024u_64u_U0' to 'start_for_FC_1u_1esQ' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'start_for_FC_1u_64u_10u_U0' to 'start_for_FC_1u_6etR' due to the length limit 20
INFO: [SYN 201-210] Renamed object name 'start_for_AXI_DMA_MASTER_U0' to 'start_for_AXI_DMAeuR' due to the length limit 20
INFO: [RTGEN 206-100] Finished creating RTL model for 'cifar_10'.
INFO: [HLS 200-111] Elapsed time: 0.61 seconds; current allocated memory: 449.345 MB.
INFO: [RTMG 210-282] Generating pipelined core: 'cifar_10_mul_32s_bkb_Mul_LUT_0'
INFO: [RTMG 210-282] Generating pipelined core: 'cifar_10_mul_32s_cud_Mul_LUT_1'
INFO: [RTMG 210-278] Implementing memory 'SCIG_inputBuf_V_ram (RAM)' using block RAMs.
INFO: [RTMG 210-278] Implementing memory 'SCIG_inElem_V_ram (RAM_S2P_LUTRAM)' using distributed RAMs.
INFO: [RTMG 210-282] Generating pipelined core: 'cifar_10_urem_7ns1iI_div'
INFO: [RTMG 210-278] Implementing memory 'SMM_1u_75u_32u_s_dEe_ram (RAM_S2P_LUTRAM)' using distributed RAMs with power-on initialization.
INFO: [RTMG 210-278] Implementing memory 'SMM_1u_75u_32u_s_eOg_ram (RAM_S2P_BRAM)' using block RAMs with power-on initialization.
INFO: [RTMG 210-278] Implementing memory 'pool_2u_32u_32u_s4jc_ram (RAM_2P_LUTRAM)' using distributed RAMs.
INFO: [RTMG 210-278] Implementing memory 'pool_2u_32u_32u_s5jm_ram (RAM_2P_LUTRAM)' using distributed RAMs.
INFO: [RTMG 210-282] Generating pipelined core: 'cifar_10_mul_32s_6jw_Mul_LUT_2'
INFO: [RTMG 210-278] Implementing memory 'SCIG_2_inputBuf_V_ram (RAM)' using block RAMs.
INFO: [RTMG 210-278] Implementing memory 'SMM_1u_800u_32u_s7jG_ram (RAM_S2P_LUTRAM)' using distributed RAMs with power-on initialization.
INFO: [RTMG 210-278] Implementing memory 'SMM_1u_800u_32u_s8jQ_ram (RAM_S2P_BRAM)' using block RAMs with power-on initialization.
INFO: [RTMG 210-278] Implementing memory 'pool_2u_32u_16u_sbVr_ram (RAM_2P_LUTRAM)' using distributed RAMs.
INFO: [RTMG 210-282] Generating pipelined core: 'cifar_10_mul_32s_bXr_Mul_LUT_3'
INFO: [RTMG 210-278] Implementing memory 'SMM_1u_800u_64u_sbZs_ram (RAM_S2P_BRAM)' using block RAMs with power-on initialization.
INFO: [RTMG 210-278] Implementing memory 'pool_2u_64u_8u_s_cNA_ram (RAM_2P_LUTRAM)' using distributed RAMs.
INFO: [RTMG 210-278] Implementing memory 'FC_1u_64u_10u_s_AdQK_ram (RAM_S2P_LUTRAM)' using distributed RAMs with power-on initialization.
INFO: [RTMG 210-278] Implementing memory 'FC_1u_64u_10u_s_BdRK_ram (RAM_S2P_BRAM)' using block RAMs with power-on initialization.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d50_A' using Block RAMs.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d50_A' using Block RAMs.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d50_A' using Block RAMs.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d50_A' using Block RAMs.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d50_A' using Block RAMs.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d50_A' using Block RAMs.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d50_A' using Block RAMs.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d50_A' using Block RAMs.
INFO: [RTMG 210-285] Implementing FIFO 'fifo_w32_d50_A' using Block RAMs.
INFO: [HLS 200-111] Finished generating all RTL models Time (s): cpu = 00:02:00 ; elapsed = 00:01:41 . Memory (MB): peak = 961.984 ; gain = 525.375 ; free physical = 13886 ; free virtual = 124333
INFO: [SYSC 207-301] Generating SystemC RTL for cifar_10.
INFO: [VHDL 208-304] Generating VHDL RTL for cifar_10.
INFO: [VLOG 209-307] Generating Verilog RTL for cifar_10.
INFO: [HLS 200-112] Total elapsed time: 101.54 seconds; peak allocated memory: 449.345 MB.
Finished C synthesis.

2.On vivado_hls2016.2

the systhesis results about cifar10 on vivado_hls 2016.2 are showed in the picture.As you can see,the using number of LUTs are 77036,and the Estimated time is 11.37ns.
why have two different results?

sorry to disturb you,but i am in mess....

[awai54st]

Hi,
HLS’s estimation of LUT usage is usually not very accurate. When you put the synthesized rtl into verilog for routing, a significant number of LUT usage can be simplified away. Please proceed to synthesize the complete using verilog, and let me know if the LUT usage remains above limit.

[sdnuzwk]

OK，let me try again，sir

[sdnuzwk]

Dear Prof，
In the previous issues,you think the simple_sum_0 and stream_mult_0 and mult_constant_0 IPS are not necessory.
I want to know if i only delete the following IPS block design （simple_sum_0 and stream_mult_0 and mult_constant_0） in vivado,will this project still work?

[sdnuzwk]

Dear Prof,
i have another question,that is the FPGA overall architecture in vivado,you can see in the picture
there are two IPS make me confuse,the one is in user ip sketchpad_v1_0,the other is in vivado_hls ip Cifar-10,so i want to know ,if i want to generate a correct bitstream,which ip i should choose?
Best wishes!

[awai54st]

Yes, removing simple_sum_0 and stream_mult_0 and mult_constant_0 will not affect the project.

[awai54st]

I think the photo you showed me is your Vivado IP repository?
I don't really know what you have synthesised so far, but all IPs generated from this project are stored in the same repository, which is the one that you are showing in this photo. So far I can see IPs from both the "graphical" and "script" design process.
In my instructions I have explained that sketchpad function is a vivado block design project for the "graphical" design process. I think you are trying to use the "script" design process instead? So that means the sketchpad function is irrelevant to you.
Please read the instructions carefully.

[sdnuzwk]

Dear Prof,
Thanks for your detail reply,thanks again.
But i want to make sure my confusion.
Question 1:
In the one hand,when i do make compile_graphical command in vivado,followed by generating the SKETCHPAD project,i think the SKETCHPAD is a CNN models for cifar-10,so i think the sketchpad_v1_0 in the UserIP is the cifar-10 IP,correct?
In the other hand,in vivado_hls,i run the following command vivado_hls -f run_cifar_10.tcl,there also can produce an IP named cifar-10,so in the Vivado IP repository has two IPS make me confused,one is the sketchpad_v1_0,the other is cifar-10,so my question is if i want to verify the cifar-10 project，is the role of these two IPS the same？
Question 2:
If i want to design my own CNN architecture
My first idea:Should i only modify the codes in vivado_hls,then i synthesise the code in vivado_hls and export the rtl ,in the next step,then a IP core of my own CNN is obtained, i just need to add this IP to the overall architeture,is my idea correct?
My second idea:Should i chaining layer blocks to design my CNN models,then package it into an IP,then a IP core of my own CNN is also obtained.
which is the correct idea?
Thank you sir .
Best wishes!

[awai54st]

Hi,
Q1. Yes the two IPs should function equivalently. The SKETCHPAD function is a vivado function designed only to package layer IPs into a complete network block design. So for graphical process this is the network IP. For script process the networks will be automatically packaged in hls projects. SKETCHPAD project is not needed for script process.
Q2. Both ideas are correct. In fact idea 1 and 2 corresponds to script and graphical process, respectively.

[sdnuzwk]

Thanks for your instructions very very much.Best best wishes!!