Comments (15)
Please specify: which part are you referring to? multiply with what?
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I use script_design_flow
Convolution in fixed_point_stream_convolution.h
Why is the output feature map of the first CONV1 output different from the CAFFE output feature map?
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For each layer, I scaled the weights and inputs with a scaling factor (to make them span the entire 8/16 bit signed int range) before casting them to fixed point for multiplication, such that the quantisation error is reduced (a somewhat inefficient implementation of "dynamic fixed point" quantisation). Hence, the output of each layer should also be scaled up as compared to the ARM benchmark, which uses floating point numbers.
So, ignoring the quantisation loss, the two output should also differ by a scaling factor.
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In HLS, my first layer of convolution is
AXI_DMA_SLAVE(in_stream, connect_0);
SCIG<3, 3, 416, 4, 416, 1> (connect_0, connect_1);
SMM<1, 27, 4>(connect_1, connect_2, 1, 0, 25);
AXI_DMA_MASTER(connect_2, out_stream);
And CAFFE's
Feat = net.blobs['conv1'].data[0, :4]
Vis_square(feat)
The output matrix gap is too large
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Your unrolling factor is 25 but the 2nd argument of SMM is 3x3x3=27. Vivado HLS expects the memory partitioning factor to be an integer factor of the memory size.
For debugging please write a HLS testbench about the first layer, and check the code’s correctness. The report provided in the repo should be enough to explain how the code works.
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If I do not use "factors", how should I write
I want to confirm whether the reason for the failure is related to factors
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The failure is probably not about the factors, but it's worth noting. You can try a factor like 3, 9, or 27 instead of 25. Regarding the source of failure, I really cannot tell based on the provided information. Please try to debug by using a testbench.
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Could you teach me how to write a test bench?
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Guide here
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I found that I changed the size of the image to 32 x 32 is the normal feature map
If the picture size is 416 x 416 it is not normal, which is why
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I found that it seems that parallelism caused
Because of the repeated transmission of data
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The problem is solved
Thanks for your help
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hi
in script_design_flow,i can find axi_dma_slave/master and they connect the first SCIG layer and the last FC layer ,but in graphic_design_flow,i cant find them.why ?thank you!
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Good to know! @DIAMONDWHILE
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Answered here.
Please do not duplicate your question on multiple issues. @wangenyi
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