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Command-line design environment for asynchronous logic

License: GNU General Public License v2.0

Makefile 1.93% C++ 86.52% Scheme 8.91% C 2.63%

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interact's Issues

v2act: rhs explisit and implisit array assign not recognised

(let me know if you rather want the clear cut act issues in the act repo)

current behavior

assignment of arrays without rage, implicitly assume the full range does not work:

module blk0(e0, out);
  input [4:0] e0;
  output [4:0] out;
  assign out = e0;
endmodule

with error message

Assertion failed, file sync.cc, line 170
Assertion: lhs == NULL
ERR: no way

it also does not like the range description (not as important):

module blk0(e0, out);
  input [4:0] e0;
  output [4:0] out;
  assign out = e0[4:0];
endmodule

with error

Parse error: Expecting token `]', got `:'
	File `./expropt0_mapped.v', line: 5, col: 25
Exception: number=1, message -none-
FATAL: Uncaught exception

proposed behavior

treat like:

module blk0(e0, out);
  input [4:0] e0;
  output [4:0] out;
  assign out = {e0[4],e0[3],e0[2],e0[1],e0[0]};
endmodule

module blk0(e0, out);
  input [4:0] e0;
  output [4:0] out;
  assign out[4]=e0[4];
  assign out[3]=e0[3];
  assign out[2]=e0[2];
  assign out[1]=e0[1];
  assign out[0]=e0[0];
endmodule

why

yosis generates this notation (the first example)

v2act: ignore "(* <comment> *)" style verilog comments

current behavior:

parsing stops for

verilog

(* module blk1 for expr *)
module blk1(a,b,out);
  output [1:0] out;
  input a,b;
  assign out[0] = b;
  assign out[1] = a;
endmodule

proposed fix:

treat like

// module blk1 for expr
module blk1(a,b,out);
  output [1:0] out;
  input a,b;
  assign out[0] = b;
  assign out[1] = a;
endmodule

reason:

yosys stores original signal names in this comment style after cell mapping in structual verilog output

v2act: namespace support for celllib

current state:

the v2act -l <celllib.act> <verilog.v> assumes the cell lib to live inside namespace sync or async.

if the cells are in a different namespace they are reported as missing modules.

celllib.act :

namespace sync {
  export defcell INVX1 (bool? A; bool! Y)
  {
    prs {
      A => Y-
    }
  }
}

verilog.v

module blk1(in,out);
  output [1:0] out;
  input [1:0] in;
  
  INVX1 cell1(.A (in[0]), .Y (out[0]));
  INVX1 cell2(.A (in[1]), .Y (out[1]));
endmodule

output:

defproc blk1 (bool? in[2], bool! out[2])
{
   /*--- types ---*/
   INVX1 cell1;
   INVX1 cell2;
  /*--- connections ---*/
   cell1(.A=in[0], .Y=out[0]);
   cell1(.A=in[1], .Y=out[1]);
}

proposed behavior:

v2act -l <celllib.act> [-n namespace::subnamespace] with default to sync/async namespace

namespace::subnamespace can be any namespace hierarchy

namespace <namespace> {
namespace <subnamespace> {
  export defcell INVX1 (bool? A; bool! Y)
  {
    prs {
      A => Y-
    }
  }
}
}

verlig.v same as above

output:

defproc blk1 (bool? in[2], bool! out[2])
{
   /*--- types ---*/
   namespace::subnamespace::INVX1 cell1;
   namespace::subnamespace::INVX1 cell2;
  /*--- connections ---*/
   cell1(.A=in[0], .Y=out[0]);
   cell1(.A=in[1], .Y=out[1]);
}

purely optional (current use case does not need it):

have the ability to define multiple namespaces in which cells sit in.

v2act: support verilog signal concat "assing c = {<a>,<b>}"

current state:

lexer stops

for verilog

module blk1(a,b,out);
  output [1:0] out;
  input a,b;
  
 assign out = {a,b};
endmodule

proposed fix:

treat like

module blk1(a,b,out);
  output [1:0] out;
  input a,b;
  
 assign out[0] = b;
 assign out[1] = a;
 
endmodule

reason

yosys uses this notation in its structural verilog output

asyncvlsi / interact Goto Github PK

interact's People

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interact's Issues

current behavior

proposed behavior

why

current behavior:

proposed fix:

reason:

current state:

proposed behavior:

purely optional (current use case does not need it):

current state:

proposed fix:

reason

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