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rtk-ntrip-rtcm

Contains program to Send RTCM3 📡 data to Hosted NTRIP server and fetch NTRIP data and display on another rover. Real time kinematic supported base and rover (Ublox-M8P) GPS units are required.

rtklib_bin

rv32firmware

Simple introduction to firmware and how tos

serval

Fork of the Serval framework

servo8bit

Servo library for the ATtiny45 and the ATtiny85

simpleexpensemanager

This is an android based basic expense manager application which will be used as a lab assignment for CS3042 - Database Systems course module.

sinhalafilmreviewindexer

Project for indexing and querying Sinhala news article based terms.

snpstools

Simple beginner tutorial for Synopsys tool chain

stopwatch-basys3

Stopwatch ⏱️ implemented using Verilog with Vivado

sweetrv

sweetRV 🧁 is a SoC with a minimal RISC-V processor with firmware for IceSugar-Nano FPGA

sweetv

FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC

tinyos

tinyos🐞: Baremetal minimal multi-tasking OS kernel for RISC-V

trafficlightcontroller

Design a sequential circuit (FSM) and implement using Verilog

treble_app_epsilon

An app which will do various stuff for Treble ROMs on Microsoft-surface duo

trojanwars

TrojanWars🐎 - Test Generation for activation of malicious hardware implants

unroll-er

Hardware Description loop Unroll-er for Verification (ex: For used in EBMC etc). Currently support Verilog

v2g

Verilog variables descriptions to graphs converting tool

vcd-toggle-counter

vendor_epsilon

visma

VISual MAth - an equation solver and visualizer (for contributing guidelines refer the CONTRIBUTING.md or wiki)

voicerecognition

xor-fpga

How I inferred XOR neural network on FPGA with 8-bits

yosysflatten

Flatten RTL hierarchy designs with Yosys