antmicro / sdi-mipi-video-converter-fpga-design

SDI to MIPI CSI-2 Video Converter FPGA design

Copyright (c) 2023 Antmicro

Introduction

This is the FPGA design for the SDI to MIPI CSI-2 Video Converter board. The design converts parallel pixel input data into MIPI CSI-2 protocol packets and synchronizes them to the MIPI D-PHY hardware interface. The conversion process is described in details in the project standalone documentation.

Content

The project consists of the following modules:

• CSI-2 Finite State Machine - FSM that controls MIPI CSI-2 protocol flow, assuming input signals FVAL/LVAL it transmits frames one by one. Underlying modules are synchronized between each other in each FSM state to strictly follow MIPI CSI-2 protocol.

• Packet Formatter (Low Level Protocol) - MIPI CSI-2 packet generator, it generates SoT (Start of Transmission), EoT (End of Transmission), header and footer for each packet.

• Checksum generator - combinatorial CRC16 checksum generator.

• TX Global Operations - controls D-PHY interface lanes switching between Low Power (LP) and High Speed (HS) modes.

• Hardened TX D-PHY - the MIPI D-PHY interface provided by the FPGA fabric, configured to operate as a transmitter, controlled by TX Global Operations.

Prerequisites

The dependencies required to build the FPGA design can be installed by running:

pip3 install -r requirements.txt

In order to generate a bitstream from the generated sources, the nextpnr toolchain is required.

Build the bitstream

Once the required tools are installed, the project can be built by invoking:

make all

There are a few additional parameters that can be added in front of the above command. See make help for more information. The generated bitstream will be available in the build/<variant> directory and it is ready to be loaded onto the FPGA device.

Software

After successful programming, the Video Converter will synchronize to SDI signal and transfer converted MIPI CSI-2 on FFC2 interface. Detailed instructions about software support is available in the SDI MIPI Video Converter documentation.

Simulation

In order to run tests with Verilator, run:

make tests

Note: Verilator tests do not cover the D-PHY module since there is no open source simulation model available.