antmicro / sdi-mipi-bridge-hw

Antmicro's open hardware 3G SDI into MIPI CSI-2 converter

SDI to MIPI CSI-2 Bridge Hardware Design

Copyright (c) 2020-2023 Antmicro

Overview

This project contains open hardware KiCad design files for Antmicro's SDI to MIPI CSI-2 bridge. This device enables connecting industrial and filmmaking cameras and video accessories to edge AI platforms which often include the MIPI CSI-2 interface.

The board includes an SDI input BNC connector and Antmicro's standard 50-pin FFC output connector (compatible with a range of our open hardware boards) exposing MIPI CSI-2 lanes as well as an I2C bus for configuration.

An additional SDI output (loopback) BNC connector is also available.

SDI signal conversion is implemented with a Semtech GS2971A deserializer which passes the parrallel 10-bit video data to the Lattice CrossLink LIF-MD6000-6KMG80I. The CrossLink FPGA includes programmable logic and dedicated MIPI D-PHY transceivers. It can be configured to accept parallel video data from the deserializer and transmit it over MIPI CSI-2 to the host platform. SPI and I2C programming interfaces are exposed so the deserializer and the CrossLink FPGA can be configured from the host platform.

Project structure

The main directory contains KiCad PCB project files, a LICENSE and README. The remaining files are stored in the following directories:

• lib - contains the component libraries
• doc - contains board schematic in PDF
• img - contains graphics for this README

Key Features

• Implements Single Link (3G-SDI) video conversion
• Supports SMPTE ST 425 (Level A and Level B), SMPTE ST 424, SMPTE ST 292, SMPTE ST 259-C and DVB-ASI as defined by the Semtec GS2971A specification
• Integrated loopback BNC connector for easy daisy-chaining with multiple SDI video accessories
• Audio de-embedder for 8 channels of 48kHz audio exposed on I2S 10 pin header
• Two 4-lane MIPI CSI-2 interfaces with up to 6 Gbps, each exposed on the 50 pin FFC connector.
• I2C configuration interface to handle CrossLink FPGA and SDI deserializer
• SPI interface for CrossLink configuration
• 12x DIP switches to initially configure the deserializer
• 2 LED indicators for user purposes

Getting started

Please refer to the SDI to MIPI CSI-2 bridge repository which aggregates the hardware design (this project), linux kernel sources, how-to documentation and reference HDL design for the CrossLink FPGA.

License

This project is licensed under the Apache-2.0 license.

sdi-mipi-bridge-hw's Issues

Buy or build help

Hi, I'am just wondering if there is a place to buy this bridge or any firm that could build it ?
Thanks for your help !

BSP supporting SDI-MIPI Bridge

Hi,
in the procedure to create the BSP for the Jetson NX, when the command "INSTALL_MOD_PATH=../Linux_for_Tegra/rootfs/ make modules_install" is sent, a message of access denied appears. If the command is sent with sudo privileges, a lot of question is asked. If all the procedure is executed like root user, all procedure work fine, but after the flash of BSP and the configuration procedure, no "/dev/video0" device is present, but the bitstream is loading correctly.

Thanks a lot

Trouble using the bridge with SD-SDI

Hi everyone.

I’m using your open source jetson baseboard and the SDI-MIPI bridge in order to convert an HD-SDI video flux from cameras and treat it with a Jetson Xavier NX module. Up until now I am very satisfied with the products.
However, I recently tried to use it with an SD-SDI input, but I am unable to get a valid video stream (the GStreamer command shows a green screen with interferences).
Is it because the deserializer or the Crosslink FPGA are unable to process an SD-SDI input stream?
Otherwise, does it has something to do with the Bitstream? It is because the 3 given ones are only compatible with an HD-SDI signal?

Also, how are the bitstreams files built? Would it be possible to access the source of the 3 provided ones?

Best regards.

v1.2.0 errata

Rework required for I2C-based gateware loading:

• Connect J6 CRESET_B to U5 pin 10 (GPIO2)
• Connect J6 USER_SDA to SDA_CL (left side of R41)
• Connect J6 USER_SCL to SCL_CL (left side of R42)

Without these changes, a programmer must be connected to J6 (the CL_PROG) header to load gateware onto the Crosslink FPGA.

Design change suggestions for the next revision:

• Add net connection between CRESET_B and U5 pin 10.
• Combine USER_SDA and SDA_CL nets
• Combine USER_SCL and SCL_CL nets