antmicro / avalanche Goto Github PK

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   LiteX port to the PolarFire Avalanche Board for Antmicro.

           Copyright 2018 / Antmicro

[> Intro
--------
This repository contains a LiteX SoC for the Microsemi PolarFire Avalanche
Evaluation board and integration of the Microsemi DDR controller.


[> Getting started
------------------
Install LiteX and Migen with the following script:
https://github.com/enjoy-digital/litex/blob/master/litex_setup.py

python3 litex_setup.py init install

Execute python3 avalanche.py to create a libero project, build it and load it
to the board.

Connect the board to a computer with the micro-USB connector, open a terminal
and you should see the LiteX Bios:
        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
 SoC BIOS / CPU: VexRiscv / 100MHz
(c) Copyright 2012-2018 Enjoy-Digital
(c) Copyright 2007-2018 M-Labs Limited
Built Nov 26 2018 15:18:58

BIOS CRC passed (5bae6eaa)
Memtest OK
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
BIOS>

Usage is similar to others LiteX SoC, to load a custom firmware to main ram:
litex_term --kernel firmware.bin /dev/ttyUSBX

[> Contact
----------
E-mail: florent [AT] enjoy-digital.fr