- ๐ Hi, Iโm Aditya Remella
- ๐ Iโm interested in VLSI Design and Verification
- ๐ฑ Iโm currently learning Verilog HDL, SystemVerilog, UVM, FPGA, CMOS
- ๐๏ธ Iโm looking to collaborate on RTL Coding, Testbench and Testcase creation
- ๐ซ How to reach me https://www.linkedin.com/in/aditya-remella-188875198/
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