AIM:
To implement 4 Bit Ripple Counter using verilog and validating their functionality using their functional tables
SOFTWARE REQUIRED:
Quartus prime
THEORY
4 Bit Ripple Counter
A binary ripple counter consists of a series connection of complementing flip-flops (T or JK type), with the output of each flip-flop connected to the Clock Pulse input of the next higher-order flip-flop. The flip-flop holding the least significant bit receives the incoming count pulses. The diagram of a 4-bit binary ripple counter is shown in Fig. below.
In timing diagram Q0 is changing as soon as the negative edge of clock pulse is encountered, Q1 is changing when negative edge of Q0 is encountered(because Q0 is like clock pulse for second flip flop) and so on.
Procedure
- Type the program in Quartus software.
- Compile and run the program.
- Generate the RTL schematic and save the logic diagram.
- Create nodes for inputs and outputs to generate the timing diagram.
- For different input combinations generate the timing diagram.
PROGRAM
RTL LOGIC FOR 4 Bit Ripple Counter
TIMING DIGRAMS FOR 4 Bit Ripple Counter
RESULTS
The 4-bit ripple counter implemented in Verilog has been successfully completed. Its functionality has been validated through simulation and comparison with the expected values from the functional tables