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View Code? Open in Web Editor NEWFPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC
License: MIT License
FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC
License: MIT License
I accidentally committed firmware/main/main_blinky.c. This file breaks the firmware build. Please delete it. Sincerest apologies.
Dear,
did you use your code and Yosys to ulitlise ICE40 blockram ?
Is the "ROM" part loaded at FPGA power up ?
Greetings,
Patrick Pelgrims
[email protected]
I'm writing a randomized testbench for your design written in python using cocotb. The test found a corner-case in spi rtl, that happens when changing spi_clk frequency from slow to fast. In this case the clock divider counts a long time and eventually wraps at 256 causing the busy-check polling loop to fail. Typically the clk_div is constant so this issue most-likely won't occur in real scenarios. The randomized test showed the bug. The fix is in the Pull Request's branch jwrr/systemverilog. Please let me know if more info is needed. thanks
Hello,
I am very interested in this project.
I tried it with the iCE40-hx8k-evn board, but it does not work as expected.
In the makefile, I changed from "TARGET = 5k" to "TARGET = 8k", no output from UART, no change LED status.
I would appreciate your advice.
Best regards.
A timer is a rather a basic peripheral needed for many tasks. Please add one.
Philipp
Today, I got an UPDuino v2.0, and I'm trying to get iceZ0mb1e to work on it. I installed the toolchain according to the README.md, connected the microUSB port, connected 5V and GND, and connected rx of a serial-to-USB-converter to pin 19 on the board.
After "make flash", the RGB LED shows a single flash for a fraction of a second. Then the green LED D2 turn on and stays on permanently. I do not see anything on the serial line.
Any idea what I could be doing wrong?
Philipp
SystemVerilog has added a do-while loop, so 'do' is now a reserved word. The TV80's Data Output bus is named 'do' which causes a compilation error when using icarus -g2012 (systemverilog partial support). I'm using cocotb for testing and it uses the -g2012 switch.
I have created a branch that changes 'do' to 'data_output'. To keep consistent naming I also changed 'di' to 'data_in'. If you're interested, I have created a pull request. Best Regards.
ps: with these changes, the simulation runs well in cocotb.
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