alexforencich / verilog-axi Goto Github PK

Many thanks for your axi-bus project.
I try to use your axi adapter ip to narrow the bus width from 256 bits to 32 bits.
It works.
Moreover, I want to further narrow the bus width from 256 bits to 8 bits.
The simulation waveform shows that the burst_reg signal is not correct.
So, could you please tell me whether the 256-to-8 configuration is supportable in your project?

Hey @alexforencich,

I'm using your axi_interconnect design to build a small SoC and I'm having an issue where a CPU is hanging due to the intcon not being available to receive more requests. The configuration for the interconnect is:

axi_interconnect_wrapper #(
    .N_MASTERS        (2),
    .N_SLAVES         (4),
    .M_BASE_ADDR      ({32'hB000_0000, 32'hA000_0000, 32'h8000_0000, 32'h1000_0000}),
    .M_ADDR_WIDTH     ({32'd17, 32'd17, 32'd17, 32'd17})
  ) u_axi_intcon (
    .clk              (clk),
    .arst             (rst_int),
    .*
  );

Basically M0 is CPU fetch I/F (only rd requests) and M1 is CPU I/F LSU, and the 4x slaves are AXI memories. I'm attaching the waves and a template for gtkwave if you can take a look and have a better guess but it's not that clear what can lead to such scenario. Also, is there a way/config to improve the interconnect throughput?

Archive.zip

Hi, Alex
Can Axi-interconnect be used in ASIC? And I want to apply it to a school teaching project.
Thanks,
Tuuyii

Can this project be compiled with VCS ？what is $from_myhdl and $to_myhdl?

I am wondering what is the maximum number of outstanding read request supported in the mmap interface of AXI in the axi_crossbar implementation. Xilinx IPs have a limit of 32 and I want something like 256.

Dear Sir,

I am trying to simulate with the testbench cocotb code with AXI_DATA_WIDTH above 64.
It went fine with 32 and 64 but failed when I set data width to 128. Not sure if the verilog module does not support it or I need to revise the Makefile and/or the test_axi_cdma.py ?

Thanks,

Brian

Hey @alexforencich,

how can I run a specific test with waves dump enabled? For instance axi_dma...

$ tox -- -k "axi_dma" WAVES=1 

Hi sir,
In axi lite interconnect, if a write operation is performed first and awvalid and awready shake hands already, but the write operation is not required , I want to start a read operation. Will the write operation be invalid and the read operation be performed?

Hi ,
I like to use AXI interconnect , I am going to connect 3 slave device to the master IO of interconnect , I want to have different base address , How to det different base address.

axi_dma_wr lines 465
if (op_word_count_reg <= AXI_MAX_BURST_SIZE - (addr_reg & OFFSET_MASK) || AXI_MAX_BURST_SIZE >= 4096) begin
// packet smaller than max burst size
https://github.com/alexforencich/verilog-axi/blob/38915fb5330cb8270b454afc0140a94489dc56db/rtl/axi_dma_wr.v#LL465C26-L465C26

If AXI_MAX_BURST_LEN set to 256 and AXI_DATA_WIDTH set to 128, the AXI_MAX_BURST_SIZE will be 4096, it will always go to the 'if' and assume the packet smaller than max burst size, if we send a data stream large than the max burst size, the axi_dma will hanging.
Did I miss some limitation of the axi_dma?

Hi, first of all excellent library, many thanks for releasing it.

Playing with axi_adapter.v going from a 256 bit wide slave to a 128 bit master.

so we have
.S_DATA_WIDTH (256),
.S_STRB_WIDTH (32),
.M_DATA_WIDTH (128),
.M_STRB_WIDTH (16),

M_ADDR_BIT_OFFSET is 4
S_ADDR_BIT_OFFSET is 5

in axi_adapter_wr/rd we have several places where this happens :
** Fatal: (vsim-3373) replay_common/lib/axi/axi_adapter_wr.v(385): Range of part-select into 's_axi_awaddr' is reversed.

s_axi_awaddr[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET])
would be:

s_axi_awaddr[3:5])

and modelsim (correctly) complains that this range is backwards.
I'm assuming the logic requires s_axi_awaddr[5:3]) in this case?

In which case I'm wondering if a pragmatic solution may be to swap the two constants over if
M_ADDR_BIT_OFFSET < S_ADDR_BIT_OFFSET

edit that doesn't work, but perhaps a H and L offset in addition to the above.

I'm guessing the simulator you are using doesn't error on this?
Best,
Mike

I tried to use the AXI_vfifo module you wrote, and I tried to configure it as a single channel FIFO. The other side is connected to a DDR MIG controller, it seems that the input of the FIFO is normal, and the AXI reading and writing of the MIG are also normal, but the FIFO has no output. I don't know where the problem lies at the moment

Hi,

I've checked out you "verilog-axi" repo (which is really cool and contains pretty much all the AXI tools) and I've found a bug in the AXIL crossbar where it doesn't support M_ADDR_WIDTH < 12. I've created a testbench with one master and 2 slaves and it works perfectly for M_ADDR_WIDTH >= 12, but asserts an error for M_ADDR_WIDTH < 12.

The root cause is in axil_register_wr.v (line 131), in axil_register_rd.v (line 119) and in axil_crossbar_addr.v (line 138). Looking at the AXIL interconnect, I've found that this limitation doesn't exist, so I copied the address check in the AXIL crossbar (M_ADDR_WIDTH[i*32 +: 32] < 0) and it works perfectly fine.

Is there any reason for not supporting M_ADDR_WIDTH < 12 ?

By the way, the AXI crossbar (not AXIL) also has the same limitation.

Thanks.

Martin Tanguay

I want to modify axil_ram.v to control block ram. But it is about two or three clock to read data from block ram. How can I modify to fit this feature?

I am getting following error during test bench execution

make -C axi_ram/. all
make[1]: Entering directory '/hdd2/verilog-axi/tb/axi_ram'
rm -f results.xml
make -f Makefile results.xml
make[2]: Entering directory '/hdd2/verilog-axi/tb/axi_ram'
rm -f results.xml
MODULE=test_axi_ram TESTCASE= TOPLEVEL=axi_ram TOPLEVEL_LANG=verilog \
         /usr/bin/vvp -M /home/apisal/.local/lib/python3.6/site-packages/cocotb/libs -m libcocotbvpi_icarus   sim_build/sim.vvp -fst
     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:78   in set_program_name_in_venv        Did not detect Python virtual environment. Using system-wide Python interpreter
     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:101  in gpi_print_registered_impl       VPI registered
     0.00ns INFO     cocotb                             Running on Icarus Verilog version 10.1 (stable)
     0.00ns INFO     cocotb                             Running tests with cocotb v1.7.2 from /home/apisal/.local/lib/python3.6/site-packages/cocotb
     0.00ns INFO     cocotb                             Seeding Python random module with 1677128929
     0.00ns CRITICAL cocotb.regression                  Failed to import module test_axi_ram: No module named 'cocotb._vendor.find_libpython'
     0.00ns INFO     cocotb.regression                  MODULE variable was "test_axi_ram"
     0.00ns INFO     cocotb.regression                  Traceback: 
     0.00ns INFO     cocotb.regression                  Traceback (most recent call last):
                                                          File "/home/apisal/.local/lib/python3.6/site-packages/cocotb/regression.py", line 189, in _discover_tests
                                                            module = _my_import(module_name)
                                                          File "/home/apisal/.local/lib/python3.6/site-packages/cocotb/regression.py", line 72, in _my_import
                                                            mod = __import__(name)
                                                          File "/home/apisal/.local/lib/python3.6/site-packages/_pytest/assertion/rewrite.py", line 171, in exec_module
                                                            exec(co, module.__dict__)
                                                          File "/hdd2/verilog-axi/tb/axi_ram/test_axi_ram.py", line 30, in <module>
                                                            import cocotb_test.simulator
                                                          File "/home/apisal/.local/lib/python3.6/site-packages/_pytest/assertion/rewrite.py", line 171, in exec_module
                                                            exec(co, module.__dict__)
                                                          File "/home/apisal/.local/lib/python3.6/site-packages/cocotb_test/simulator.py", line 13, in <module>
                                                            import cocotb._vendor.find_libpython as find_libpython
                                                        ModuleNotFoundError: No module named 'cocotb._vendor.find_libpython'
                                                        
     0.00ns ERROR    gpi                                Passing event to upper layer failed
/home/apisal/.local/lib/python3.6/site-packages/cocotb/share/makefiles/simulators/Makefile.icarus:75: recipe for target 'results.xml' failed
make[2]: Leaving directory '/hdd2/verilog-axi/tb/axi_ram'
/home/apisal/.local/lib/python3.6/site-packages/cocotb/share/makefiles/Makefile.inc:39: recipe for target 'sim' failed
make[1]: Leaving directory '/hdd2/verilog-axi/tb/axi_ram'
Makefile:27: recipe for target 'axi_ram/.' failed

I'm using the axis_fifo_adapter with an input data width of 32 and output data width of 8. I was surprised to see that the output data stream seems to come out in little endian. For example if the input data word is "DEAD_BEEF", it's coming out of the FIFO as "EF", "BE", "AD", "DE".

Is this by design? I would have expected the fifo to use Netowrk byte order or have an option to do that. Am I doing something wrong?

Hello, I found that the "priority_encoder" was optimized out when synthesizing "axi_interconnect" using Vivado. Do you know the reason behind this?
The following image shows the synthesis schematic results:

Hey @alexforencich,

about the axi_interconnect module, could you give an example of how to create the memory map of masters / slaves using your design? I'm bit confused of how to define it like exists for instance in the bus matrix from ARM. Basically in the bus matrix you have a xml where you define the relation between m+s and then generates the design of the interconnect, in your case I suppose we handle the parameters of the design, but how exactly I can tweak it to have a scenario like this:

  __________________
| 0x0000 | slave # 0 |
| 0x1000 | slave # 1 |
| 0x4000 | slave # 2 |
| 0x5000 | slave # 3 |
| 0x6000 | slave # 4 |
  ⎻⎻⎻⎻⎻⎻⎻⎻⎻⎻⎻⎻⎻⎻⎻⎻⎻⎻

I'm planning to use your DMAs in a high performance design. Since DDR delivers data after several clocks, it would be ideal if the DMA can issue multiple outstanding AXI transactions, without waiting for each transaction to complete.

Is this feature already included? Or are you planning to add it in the future?

Btw, thanks a lot for this amazing repo!!

Hey @alexforencich,

thanks for the IPs, such amazing job for the open source community! I have a question for you about the axi_dma design, basically from my understanding the write descriptors interface (s_axis_write_desc_*) configures the way the s_axis_write_data* will be reflected/processed in the m_axi_aw/w channels so if you see the image below, in this test, the descriptor length is 7 bytes. I see that in the write address channel you launch a two beat burst due to fact you can only send 4 bytes per beat. Although in the write data channel I see that you only send 5 bytes, is this because the randomisation of the test didn't set the other 2x tkeep bits and you just mirror the same in the write data channel or am I missing something? why the descriptor finishes with only 5 bytes transferred?

Dear Alex,
I have a question about the module of axi_ram. When you use "initial begin end " to initialize the mem[(2**VALID_ADDR_WIDTH)-1:0], should you use "VALID_ADDR_WIDTH" instead of "ADDR_WIDTH"? The attached files is more explict. I am looking for your answer.Thanks!

AXI specification requires a WID signal which should match AWID of the corresponding address.

Edit: My fault that I missed that AXI4 removed this signal.

I took some time to understand the code below and has the following question

for (i = 0; i < M_COUNT; i = i + 1) begin for (j = 0; j < M_REGIONS; j = j + 1) begin if (M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32] && (!M_SECURE[i] || !axi_prot_reg[1]) && ((read ? M_CONNECT_READ : M_CONNECT_WRITE) & (1 << (s_select+i*S_COUNT))) && (axi_addr_reg >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32]) == (M_BASE_ADDR_INT[(i*M_REGIONS+j)*ADDR_WIDTH +: ADDR_WIDTH] >> M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32])) begin m_select_next = i; axi_region_next = j; match = 1'b1; end end end

May I know why it is necessary to have a long if condition list? For example...

M_ADDR_WIDTH[(i*M_REGIONS+j)*32 +: 32] <==This will be always TRUE no matter how as long as user define those parameters.

((read ? M_CONNECT_READ : M_CONNECT_WRITE) <== This will be always TRUE as well.

I might be wrong in my interpretation.
If you don't mind, could you please share probably they is a strong reason to have this checking?

Hi,

This is a nice library, but I think the reset signals should be active low as defined by the protocol.

Cheers

Hi Alex,

Do you plan to add support for "auto" clock domain crossing between master and slaves? E.g. I have multiple slaves that operate in different domains of each other. Now, all my writing and reading of register in the slave needs to go through CDC as the AXI bus is operating in another domain. However, if the bus itself were CDC'd for each slave in another domain than the master, a lot of hassle could be avoided. I also think I would save a lot of resources.

I understand completely if this is far fetched :)

Ola

Hi @alexforencich
when i read the file axi_cdma.v , I have a question about the data transfer order. when output is not ready , data will be stored in the temp. When output is ready in the next cycle, the data in temp should be sent to the output first. But in line 773, int_to_output has the highest priority, and the input data is sent directly to output, skipping the data in temp.
The reg m_axi_wready_int_reg is only associated with input status，so I wonder if there's a problem with the logic here.

(line 773,axi_cdma.v)

if (m_axi_wready_int_reg) begin
    // input is ready
    if (m_axi_wready || !m_axi_wvalid_reg) begin
        // output is ready or currently not valid, transfer data to output
        m_axi_wvalid_next = m_axi_wvalid_int;
        store_axi_w_int_to_output = 1'b1;
    end else begin
        // output is not ready, store input in temp
        temp_m_axi_wvalid_next = m_axi_wvalid_int;
        store_axi_w_int_to_temp = 1'b1;
    end
end else if (m_axi_wready) begin
    // input is not ready, but output is ready
    m_axi_wvalid_next = temp_m_axi_wvalid_reg;
    temp_m_axi_wvalid_next = 1'b0;
    store_axi_w_temp_to_output = 1'b1;
end

None of the components currently support read data interleaving. I think the only module this affects is the AXI crossbar.

Verilator complains about circular logic in several places.
I believe most of them are false positive, but I'm not sure about this one, thread_trans_start:

Dear Alex,
I have a question about the module of axi_ram. When you use "initial begin end " to initialize the mem[(2**VALID_ADDR_WIDTH)-1:0], should you use "VALID_ADDR_WIDTH" instead of "ADDR_WIDTH"? The attached files is more explicit. I am looking forward to your answer.Thanks!

Hi, Sir. I am studying the priority_encoder module and I have some confusion about the following code. I would appreciate it if you could provide me with some explanation

// compress down to single valid bit and encoded bus
for (l = 1; l < LEVELS; l = l + 1) begin : loop_levels
    for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress
        assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];//compress down to single valid.
        if (LSB_HIGH_PRIORITY) begin
            // bit 0 is highest priority
            assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};
        end else begin
            // bit 0 is lowest priority
            assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
        end
    end
end

Q1:Why do you use the value of stage_valid[l-1][n2+0] to make the selection when LSB_HIGH_PRIORITY is set to 1? I believe that in the code above, you compressed two requests into one valid value with the line "assign stage_valid[0][n] = |input_padded[n2+1:n2];", so why do you skip the odd bit and use the [n2+0] bit here? What I understand is that when LSB_HIGH_PRIORITY is set to 1, it means that the priority is given to the lower bits. However, I don't see the relation between this code and the priority.

Q2：When Width is 4, LEVELS equals 2. Then 'stage_enc[l][(n+1)(l+1)-1:n(l+1)]' is 2 bits, and '{1'b0, stage_enc[l-1][(n*2+1)l-1:(n2+0)*l]}' is 3 bits. This means that the bit width is not matched. Am I misunderstanding something?

I am using AXI DMA and AXI RAM to implement a on-chip RAM accessed through DMA engine.
The files I used are axi_dma.v, and axi_ram.v

The problem is that I found s_axis_write_desc_ready and s_axis_read_desc_ready coming from the DMA engine were always 0 no matter what inputs I gave into.

This is a screenshot of how I generate the AXI_DMA module and connect them to the outside world. I made write_enable always be 1 but still failed

Any ideas about what would possibly be the reasons?

Thank you

Hi, @alexforencich

I am doing a formal verificaion for verilog-axi IPs, see my repo verilog-axi-formal. And I found an AXI4 lite handshake issue with axil_ram interface, the aw/w-ready is assert with bvalid at the same clock, see the code below

And the AXI standard says,

the slave must wait for both WVALID and WREADY to be asserted before asserting BVALID
An explain from https://community.arm.com/ is here
Which means bvalid should at least one clock after wready.

there are the same error when I sim the tb module or make all clean.
`make: Entering directory “/home/ICer/ic_prjs/github_AXI_prj/verilog-axi-master/tb/axi_adapter”
rm -f results.xml
make -f Makefile results.xml
make[1]: Entering directory “/home/ICer/ic_prjs/github_AXI_prj/verilog-axi-master/tb/axi_adapter”
mkdir -p sim_build
/usr/local/bin/iverilog -o sim_build/sim.vvp -D COCOTB_SIM=1 -s axi_adapter -P axi_adapter.M_DATA_WIDTH=32 -P

axi_adapter.ADDR_WIDTH=32 -P axi_adapter.BUSER_WIDTH=1 -P axi_adapter.CONVERT_BURST=1 -P axi_adapter.WUSER_WIDTH=1 -P axi_adapter.BUSER_ENABLE=0 -P axi_adapter.FORWARD_ID=1 -P axi_adapter.WUSER_ENABLE=0 -P axi_adapter.S_STRB_WIDTH=4 -P axi_adapter.RUSER_WIDTH=1 -P axi_adapter.ARUSER_WIDTH=1 -P axi_adapter.S_DATA_WIDTH=32 -P axi_adapter.AWUSER_WIDTH=1 -P axi_adapter.CONVERT_NARROW_BURST=1 -P axi_adapter.RUSER_ENABLE=0 -P axi_adapter.ID_WIDTH=8 -P axi_adapter.M_STRB_WIDTH=4 -P axi_adapter.ARUSER_ENABLE=0 -P axi_adapter.AWUSER_ENABLE=0 -f sim_build/cmds.f -g2012 ../../rtl/axi_adapter.v ../../rtl/axi_adapter_wr.v ../../rtl/axi_adapter_rd.v

rm -f results.xml
MODULE=test_axi_adapter TESTCASE= TOPLEVEL=axi_adapter TOPLEVEL_LANG=verilog
/usr/local/bin/vvp -M /usr/local/lib64/python3.6/site-packages/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp -fst
-.--ns INFO gpi ..mbed/gpi_embed.cpp:78 in set_program_name_in_venv Did not detect Python virtual environment. Using system-wide Python interpreter
-.--ns INFO gpi ../gpi/GpiCommon.cpp:101 in gpi_print_registered_impl VPI registered
FST support disabled since zlib not available
make[1]: *** [/usr/local/lib64/python3.6/site-packages/cocotb/share/makefiles/simulators/Makefile.icarus:95：results.xml] error 1
make[1]: Leaving directory “/home/ICer/ic_prjs/github_AXI_prj/verilog-axi-master/tb/axi_adapter”
make: *** [/usr/local/lib64/python3.6/site-packages/cocotb/share/makefiles/Makefile.inc:40：sim] error 2
make: Leaving directory “/home/ICer/ic_prjs/github_AXI_prj/verilog-axi-master/tb/axi_adapter”`

I have installed:
$ pip3 install cocotb
$ pip3 install cocotb-bus
$ pip3 install cocotb-test
$ pip3 install cocotbext-axi
$ pip3 install cocotbext-eth
$ pip3 install cocotbext-pcie
$ pip3 install pytest
$ pip3 install scapy
$ pip3 install tox
$ pip3 install pytest-xdist
$ pip3 install pytest-sugar

the python version is 3.6
cocotb version is 1.8.0

So what should I to do for these errors?

update python version?

please

Hi @alexforencich ,
I have seen the file axi_ram.v, but I didn't see the use of s_axi_wlast.
Could u tell me the reason ?

In axi_dma_rd.v and axi_dma_wr.v

Take axi_dma_rd.v as an example:

339         AXI_STATE_START: begin
340             // start state - initiate new AXI transfer
341             if (!m_axi_arvalid) begin
342                 if (op_word_count_reg <= AXI_MAX_BURST_SIZE - (addr_reg & OFFSET_MASK) || AXI_MAX_BURST_SIZE >= 4096) begin
343                     // packet smaller than max burst size
344                     if (addr_reg[12] != addr_plus_count[12]) begin
345                         // crosses 4k boundary
346                         tr_word_count_next = 13'h1000 - addr_reg[11:0];
347                     end else begin
348                         // does not cross 4k boundary
349                         tr_word_count_next = op_word_count_reg;
350                     end
351                 end else begin
352                     // packet larger than max burst size
353                     if (addr_reg[12] != addr_plus_max_burst[12]) begin
354                         // crosses 4k boundary
355                         tr_word_count_next = 13'h1000 - addr_reg[11:0];
356                     end else begin
357                         // does not cross 4k boundary
358                         tr_word_count_next = AXI_MAX_BURST_SIZE - (addr_reg & OFFSET_MASK);
359                     end
360                 end

Line 342, if setting AXI_MAX_BURST_SIZE = 4096, which is the maximum number defined in AXI4 spec, line 342 always returns "true", and then no matter what the remaining length is, the packet is treated as "smaller than max burst size". That means the last burst beat with possible invalid bytes masked by strobe (for write) or ignored (for read).

This issue can be fixed by changing ">=" to ">" or completely removing the expression of || AXI_MAX_BURST_SIZE >= 4096.

Hi,I have some problems about the AXI_DMA module,what does parameter OFFSET_WIDTH,OFFSET_MASK,ADDR_MASK and CYCLE_COUNT_WIDTH mean?Can I ask you for a AXI_DMA_RD_TB.V and AXI_DMA_WR_TB.V file？Maybe can help me understand this module,thanks.

hey sir :
I just start learning axi stuff, when i read pg059-axi-interconnect [xilinx], im confused about 'Avoiding Deadlock Using Single Slave Per ID', i want to know if you implement this function in axi crossbar? and what part of the code achieved that?
Thanks a lot.

Hi, sir
I have tried to write CDC module, and I understand how to write async FIFO(using gray code), but I don't know how to make axi-full interface. For example, how should ID signals and address signals be saved in async FIFO?
And may I take the liberty to ask if you could write axi-full cdc first? ToT

Hi, this isnt an issue, it's a question, about verilog, since you're using a notation I haven't seen before, and not quite sure how to Google.

At e.g.

reg [7:0] m_axi_awlen_reg = 8'd0, m_axi_awlen_next;

So, I'm interpreting this to mean that, you create an 8 bit register m_axi_awlen_reg, and assign it the value of m_axi_awlen_next. However, I'm not sure what the 8'd0, does? I'm guessing it does something like assert the number of bits in m_axi_awlen_next? (I looked through verilog-std-1364-2005.pdf, eg section 6.2, 9.2, but wasn't able to find the relevant syntax).

Simulator: Modelsim

Tb connection:
axi4lite-master-bfm <-> axil_adapter <-> axil_ram

In simulation I found error:
" ** Fatal: (vsim-3373) /home/peio/fpgawork/cores/verilog-axi/rtl/axil_adapter_wr.v(215): Range of part-select into 'm_axil_awaddr_reg' is reversed."

axil_adapter_wr.v(215) is:
m_axil_wstrb_next = s_axil_wstrb << (m_axil_awaddr_reg[M_ADDR_BIT_OFFSET - 1:S_ADDR_BIT_OFFSET] * S_STRB_WIDTH);

M_ADDR_BIT_OFFSET=2
S_ADDR_BIT_OFFSET=2

simulator doesn't like m_axil_awaddr_reg[1:2]
is it a bug in axil_adapter_wr?

axi_ram module triggers a AXI protocol violation bit 32 in Xilinx AXI Protocol Checker

To be more exact, it is related to the BVALID logic implementation in the AXI slave.

Could you advise ?

Attached : AXI.zip

The data_width parameter is constant 32 in the tests according to logs, despite it having been defined to take values from the [8, 16, 32] range.

 90890.02ns INFO     AXI lite master configuration:
 90890.02ns INFO       Address width: 32 bits
 90890.02ns INFO       Byte size: 8 bits
 90890.02ns INFO       Data width: 32 bits (4 bytes)
 90890.02ns INFO     AXI lite master signals:
 90890.02ns INFO       awaddr width: 32 bits
 90890.02ns INFO       awprot width: 3 bits
 90890.02ns INFO       awready width: 1 bits
 90890.02ns INFO       awvalid width: 1 bits
 90890.02ns INFO       wdata width: 32 bits
 90890.02ns INFO       wready width: 1 bits
 90890.02ns INFO       wstrb width: 4 bits
 90890.02ns INFO       wvalid width: 1 bits
 90890.02ns INFO       bready width: 1 bits
 90890.02ns INFO       bresp width: 2 bits
 90890.02ns INFO       bvalid width: 1 bits

Logs for all tests show 32-bit data width.

I am a newbie to axi-lite. I was trying to mimic the example figure in the documentation.
I have 1x1 crossbar. My master awchannel and wchannel are the following. From the slave side I assign awready and wready to 0. But I see these signals asserts themselves in master. Is it bug, or am I missing something?

// w_en signal is external signal from testbench.
// aw channel
always_ff @(posedge clk) begin
   if (rst) begin
		awaddr  <= 32'h0;
		awvalid <= 1'b0;
		su_addr <= DEFAULT_VAL;
   end
	else if(w_en) begin
		awvalid <= 1'b1;
		awaddr <= su_addr;
	end
	else awvalid <= 1'b0;
end 

// wchannel
always_ff @(posedge clk) begin
   if(rst) begin
		wvalid <= 1'b0;
		su_data <= DEFAULT_VAL;
	end
   else if(w_en) begin
		 wvalid <= 1'b1;
		 wdata <= su_data;
	  end
	else wvalid <= 1'b0;
end

Hi Mr Forencich,

First of all, thank you very much for all your work on this repository and for publishing this.

I'm currently trying tu use your axil_interconnect IP in a N to 1 configuration, in order to connect several Masters outputs to a single Slave input.

However, I have a problem using this module. I tried to do a test-bench with Cocotb with the following setup for the axil_interconnect component :

S_COUNT = 2,
M_COUNT = 1,
DATA_WITH = 32,
ADDR_WIDTH = 32,
M_BASE_ADDR = 0,
M_ADDR_WIDTH = 32

In the Cocotb test-bench I then defined 2 AxiLiteMaster connected to the 2 input ports and an AxiLiteRam on the output bus. But during the execution of the test, it blocks when writing on the input ports.

I guess I'm setting up the parameters wrong, I'm having trouble understanding the purpose of M_BASE_ADDR and M_ADDR_WIDTH. Could you please give me some advice on how to get the AXI Lite interconnect to work in an N to 1 configuration?

Thanks in advance :)

Hi, sir
I have some questions about the synchronization techniques.

1. Is your axil-CDC implemented with dual latches? Or MCP formulation?

2. I want to implement a axi-full cdc module. so, for AXI-Full , is clock domain synchronization implemented using an asynchronous FIFO?

Sorry to bother you. ^ ^. I'm a little weak on the basics, so I'm hoping for your help badly! Thank you!
Best wishes.

Hi another question (and also curious):

Why dma_wr uses a different structure to dma_rd on the generation of status_len/tag?
dma_wr uses status_fifo, but dma_rd doesn't.

My recent synthesis tells me that it has 16 logic levels. It's a challenge for 300MHz+.

Max Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) :        -1.535ns  (required time - arrival time)
  Source:                 u_fpga/u_net_wrapper/u_udp_aximm_write/axi_dma_wr_inst/offset_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by txoutclk_out[0]  {[email protected] [email protected] period=3.103ns})
  Destination:            u_fpga/u_net_wrapper/u_udp_aximm_write/axi_dma_wr_inst/status_fifo_len_reg_0_31_0_13/RAMF_D1/I
                            (rising edge-triggered cell RAMD32 clocked by txoutclk_out[0]  {[email protected] [email protected] period=3.103ns})
  Path Group:             txoutclk_out[0]
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.103ns  (txoutclk_out[0] [email protected] - txoutclk_out[0] [email protected])
  Data Path Delay:        4.406ns  (logic 1.681ns (38.153%)  route 2.725ns (61.848%))
  Logic Levels:           16  (CARRY8=2 LUT2=1 LUT3=1 LUT4=2 LUT5=3 LUT6=7)
  Clock Path Skew:        -0.105ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.522ns = ( 6.625 - 3.103 )
    Source Clock Delay      (SCD):    3.931ns
    Clock Pessimism Removal (CPR):    0.304ns
  Clock Uncertainty:      0.046ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.060ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.716ns (routing 1.706ns, distribution 2.010ns)
  Clock Net Delay (Destination): 3.330ns (routing 1.550ns, distribution 1.780ns)

dma_rd.v only generates status_tag output. I used the same way to generate status_len (this is important to count how many bytes has been transferred) and it looks much simpler than the status_fifo in dma_wr.v

Hey @alexforencich,

for the axi_ram.v design, do you have a version with the macros instantiations (BRAM_SDP_MACRO/BRAM_TDP_MACRO) or a tip to force bram inference by Vivado? I'm actually suffering with Vivado consuming LUT RAMs instead of BRAMs for my memories in the design....I suppose only adding (* ram_style = "block" *) will not force the inference once the design doesn't follow "Xilinx pattern of design".

Hi Alex,

Where to find a verilog axi4 synthesizable protocol checker?

Thanks,

David

I am using the latest Version of cocotbext-axi.

In my code I am using

AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axi_if"), dut.clk_i, dut.reset_ni, reset_active_level = False)

This is working when I simulate it with iverilog but it hangs with Verilator.

I am using axil_interconnect with this configuration (ADDRESS_WIDTH = 16)

axil_interconnect_wrap_1x4 #(
    .DATA_WIDTH(32),
    .ADDR_WIDTH(ADDRESS_WIDTH),
    .M_REGIONS(1),
    .M00_ADDR_WIDTH(ADDRESS_WIDTH),
    .M01_ADDR_WIDTH(ADDRESS_WIDTH),
    .M02_ADDR_WIDTH(ADDRESS_WIDTH),
    .M03_ADDR_WIDTH(ADDRESS_WIDTH),
    .M00_BASE_ADDR(16'h1000),
    .M01_BASE_ADDR(16'h2000),
    .M02_BASE_ADDR(16'h3000),
    .M03_BASE_ADDR(16'h4000)
)

I am getting this error

INFO cocotb: Region not aligned:
INFO cocotb:  0 ( 0): 1000 / 16 -- 0000-ffff

Is there somewhere a documentation how the parameters of this core work?