zqayra,github

32-verilog-mini-projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

5g-ldpc

5g ldpc codes

5g-nr-ldpc

5G NR LDPC MATLAB implementation

5g-nr-ldpc-1

A 3GPP 5G NR compliant LDPC library.

5g_iitm

Matlab codes for course "LDPC and Polar Codes in 5G Standard" by IITM. Coded by Teddy van Jerry.

802.11n-ldpc

A matlab implementation of the 802.11n LDPC encoder and decoder

aic2021_tpu_template

Template for project1 TPU

amba_axi_ahb_apb

AMBA bus lecture material

asynchronous-fifo

Asynchronous fifo in verilog

axis_udp

This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core

channelcodingprojectlist

List of open source channel coding projects and libraries.

computer-architecture

Hardware designs modelled with verilog

convolution-using-systolic-arrays

design-and-verification-of-ldpc-decoder

- Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and parallel architecture. - Created modules for all variants of the variable node unit(VNU) and the check-node unit(CNU) based on the H matrix. Created script for module instantiation of VNU and CNU as per the H matrix. - Verified the functionality of the Verilog implementation by self-checking test-bench in Verilog to compare the results with Matlab.

digital_ic_design_notes

数字IC设计学习笔记

ee599_yihaowang_7410178057

EE599 Accelerated Computing on FPGA

ethernet-design-verilog

Gigabit Ethernet UDP communication driver

ethernet-fmc-processorless

Example designs for using Ethernet FMC without a processor (ie. state machine based)

fifo_-asynchronous

异步FIFO的内部实现

fpga

数字IC相关资料

fpga-ethernet

UDP frames Tx/Rx via Ethernet

fpgaandperipheralinterface

Peripheral Interface of FPGA

genetic-algorithm-based-ldpc-code-design

Source code from the paper: A. Elkelesh, M. Ebada, S. Cammerer, L. Schmalen, and S. ten Brink, “Decoder-in-the-Loop: Genetic Optimization-Based LDPC Code Design,” in IEEE Access, 2019.