Makefile:82: recipe for target 'obj_dir/Vmain.h' failed about zbasic

[ZipCPU]

I think I found/fixed all of the issues. Please try another pull to see if things have been fixed.

The issues were:

1. The meaning of the WBUART busy bit had changed. As a result, _uart->u_fifo & 0x010000 would only be true if the transmitter was busy, not if it was idle. Hence the CPU would load up and wait for the idle transmit port to become busy before sending a character. Both cputest.c and syscalls.c have been updated to reflect this change.
2. The "gie" register in dcache.v is only used in piped mode. This mode is set by defining OPT_PIPELINED_BUS_ACCESS in rtl/cpu/cpudefs.v. (I recommend setting it, and I almost always run with this option set--hence I never caught this bug.) The dcache has been updated so that the wire is now driven--even if OPT_PIPELINED_BUS_ACCESS isn't set. Only, if it isn't set, the value is silently ignored. You were able to run successfully before, because I've set Verilator to die on any warnings not just on errors. When it dies, however, it leaves behind its partial build products. Running a second time builds these into a design. In this case, it would've been a working design too.

Feel free to go ahead and do a git pull and let me know what happens. Your error should now be fixed.

Dan

[NeuerUser]

Hi Dan

Thanks for your reply. I made clean the working directory, checked out the new commits, verified that my copy is completely clean and tried a new make. This time I get a new error message:

$ make
tar --transform s,^,`date +%Y%m%d`-zbasic/, -chjf `date +%Y%m%d`-zbasic.tjz  `find sw -name "*.cpp"` `find sw -name "*.c"` `find sw -name "*.h"`        `find sw -name "*.sh"` `find sw -name "*.py"`        `find sw -name "*.pl"` `find sw -name "*.png"`  `find sw -name Makefile` `find rtl -name "*.v"` `find rtl -name Makefile` `find sim -name Makefile` `find sim -name "*.cpp"` `find sim -name "*.h"` `find sim -name "*.c"` `find . -name "*.txt"` `find . -name "*.html"`   `find . -name "*.xdc"` `find auto-data -name "*.txt"` README.md
verilator -Wall --MMD -O3 --trace -Mdir ./obj_dir -y cpu -cc main.v
make --no-print-directory -C obj_dir -f Vmain.mk
/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vmain.cpp > Vmain__ALLcls.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow       -c -o Vmain__ALLcls.o Vmain__ALLcls.cpp
/usr/bin/perl /usr/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vmain__Dpi.cpp Vmain__Trace.cpp Vmain__Syms.cpp Vmain__Trace__Slow.cpp > Vmain__ALLsup.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -faligned-new -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow       -c -o Vmain__ALLsup.o Vmain__ALLsup.cpp
      Archiving Vmain__ALL.a ...
ar r Vmain__ALL.a Vmain__ALLcls.o Vmain__ALLsup.o
ar: Erzeugen von Vmain__ALL.a
ranlib Vmain__ALL.a
Building cpudefs.h
Building design.h
Building dependency file
g++ -Og -g -Wall -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -DNEW_VERILATOR -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -c main_tb.cpp -o obj-pc/main_tb.o
In file included from main_tb.cpp:56:0:
testb.h: In instantiation of ‘TESTB<VA>::TESTB() [with VA = Vmain]’:
main_tb.cpp:177:15:   required from here
testb.h:58:12: warning: ‘new’ of type ‘Vmain’ with extended alignment 128 [-Waligned-new=]
   m_core = new VA;
            ^~~~~~
testb.h:58:12: note: uses ‘void* operator new(std::size_t)’, which does not have an alignment parameter
testb.h:58:12: note: use ‘-faligned-new’ to enable C++17 over-aligned new support
g++ -Og -g -Wall -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -DNEW_VERILATOR -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -c automaster_tb.cpp -o obj-pc/automaster_tb.o
In file included from automaster_tb.cpp:51:0:
testb.h: In instantiation of ‘TESTB<VA>::TESTB() [with VA = Vmain]’:
main_tb.cpp:177:15:   required from here
testb.h:58:12: warning: ‘new’ of type ‘Vmain’ with extended alignment 128 [-Waligned-new=]
   m_core = new VA;
            ^~~~~~
testb.h:58:12: note: uses ‘void* operator new(std::size_t)’, which does not have an alignment parameter
testb.h:58:12: note: use ‘-faligned-new’ to enable C++17 over-aligned new support
g++ -Og -g -Wall -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -DNEW_VERILATOR -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -c flashsim.cpp -o obj-pc/flashsim.o
g++ -Og -g -Wall -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -DNEW_VERILATOR -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -c sdspisim.cpp -o obj-pc/sdspisim.o
g++ -Og -g -Wall -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -DNEW_VERILATOR -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -c dbluartsim.cpp -o obj-pc/dbluartsim.o
g++ -Og -g -Wall -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -DNEW_VERILATOR -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -c zipelf.cpp -o obj-pc/zipelf.o
g++ -Og -g -Wall -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -DNEW_VERILATOR -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -c byteswap.cpp -o obj-pc/byteswap.o
g++ -Og -g -Wall -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -c /usr/share/verilator/include/verilated.cpp -o obj-pc/verilated.o
g++ -Og -g -Wall -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -c /usr/share/verilator/include/verilated_vcd_c.cpp -o obj-pc/verilated_vcd_c.o
g++ -I../../sw/host -I../../rtl -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I../../rtl/obj_dir -DNEW_VERILATOR obj-pc/main_tb.o obj-pc/automaster_tb.o obj-pc/flashsim.o obj-pc/sdspisim.o obj-pc/dbluartsim.o obj-pc/zipelf.o obj-pc/byteswap.o obj-pc/verilated.o obj-pc/verilated_vcd_c.o ../../rtl/obj_dir/Vmain__ALL.a ../../rtl/obj_dir/Vmain__ALL.a -lelf -o main_tb
make --no-print-directory -C sw/host
g++ -g -Wall -I. -I../../rtl -c zipload.cpp -o obj-pc/zipload.o
In file included from zipload.cpp:55:0:
ttybus.h: In destructor ‘virtual TTYBUS::~TTYBUS()’:
ttybus.h:110:3: warning: this ‘if’ clause does not guard... [-Wmisleading-indentation]
   if (m_buf) delete[] m_buf; m_buf = NULL;
   ^~
ttybus.h:110:30: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the ‘if’
   if (m_buf) delete[] m_buf; m_buf = NULL;
                              ^~~~~
g++ -g obj-pc/zipload.o obj-pc/flashdrvr.o obj-pc/ttybus.o obj-pc/llcomms.o obj-pc/regdefs.o obj-pc/byteswap.o obj-pc/zipelf.o -lelf -o zipload
Building dependency file(s)
zip-gcc -O3 -I. -I../../rtl -c udiv.c -o obj-zip/udiv.o
zip-gcc -O3 -I. -I../../rtl -c umod.c -o obj-zip/umod.o
zip-gcc -O3 -I. -I../../rtl -c syscalls.c -o obj-zip/syscalls.o
zip-gcc -O3 -I. -I../../rtl -ffreestanding -c crt0.c -o obj-zip/crt0.o
zip-ar -cru libzbasic.a obj-zip/udiv.o obj-zip/umod.o obj-zip/syscalls.o obj-zip/crt0.o
Building dependency file(s)
zip-gcc -O3 -c hello.c -o obj-zip/hello.o
make[1]: *** Keine Regel vorhanden, um das Ziel „/home/dan/work/rnd/zipcpu/sw/install/cross-tools/zip/lib/libg.a“, 
  benötigt von „hello“, zu erstellen.  Schluss.
Makefile:182: recipe for target 'sw-board' failed
make: *** [sw-board] Error 2

That seems to be that line in the makefile that is involved here:

INSTALLD=/home/dan/work/rnd/zipcpu/sw/install

I tried changing the path, but that will lead to the same error message just with the new path, namely that there is no rule for that target.

[ZipCPU]

Yes, you will need to change the path to reflect the install directory for your ZipCPU tool chain. In my case, my ZipCPU installation is found in /home/dan/work/rnd/zipcpu and the sw/install directory is created by building the ZipCPU tools in the sw/ directory. You should also be able to find the missing libg.a file in cross-tools/zip/lib/libg.a.

Let me know if you don't have a libg.a file, and we can chase that down from there. (You should have it.)

As for the warnings:

1. The "extended alignment" issue is (for now) just a warning. The change necessary to fix it would break the install on older machines.
2. The ttybus errors are worth fixing. The design will work with or without fixing them, but I can take an action to fix that. The compiler is right--there should be some {}'s in there.

Dan

[NeuerUser]

Great! It works! Very nice. Thanks a lot. Now I can try to play around with it and see if I can grasp at least partly how this all interacts.
Although my main goal is not to become an FPGA designer. (I guess, I am too old for that.) I will be very happy to try to understand your great framework and toolset and hopefully be able to implement something on my board.