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ysong233's Projects

axi icon axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

clarvi icon clarvi

Clarvi simple RISC-V processor for teaching

cnrv-fpu icon cnrv-fpu

Basic floating-point components for RISC-V processors

compiler-explorer icon compiler-explorer

Run compilers interactively from your web browser and interact with the assembly

corundum icon corundum

Open source FPGA-based NIC and platform for in-network compute

cursor icon cursor

An editor made for programming with AI 🤖

darkriscv icon darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

e200_opensource icon e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

esp-idf icon esp-idf

Espressif IoT Development Framework. Official development framework for Espressif SoCs.

excalidraw-cn icon excalidraw-cn

支持中文手绘效果和多画布能力的 Excalidraw。Support Chinese hand draw effect and multi canvas based on Excalidraw.

f32c icon f32c

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

freedom icon freedom

Source files for SiFive's Freedom platforms

hidden-two-stream icon hidden-two-stream

Caffe implementation for "Hidden Two-Stream Convolutional Networks for Action Recognition"

home icon home

为推广RISC-V尽些薄力

hw icon hw

RTL, Cmodel, and testbench for NVDLA

ibex icon ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

interview icon interview

Interview = 简历指南 + 算法题 + 八股文 + 源码分析

ipodrpi icon ipodrpi

Classic iPod mod with Raspberry Pi Zero and color screen

kamikaze icon kamikaze

Light-weight RISC-V RV32IMC microcontroller core.

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