Comments (8)
I'm facing similar issue with version 0.38 on similar code
I had to change your verilog to get it to compile with sby
module counter(input clk, input rst, output reg [7:0] count);
always @(posedge clk or posedge rst) begin
if (rst)
count <= 0;
else
count <= count + 1;
end
always @(posedge rst)
assert property ( count == 0);
endmodule // counter
from sby.
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from sby.