`nextpnr-ice40` is failing to route PLL clock about nextpnr

[smunaut]

@cr1901 Do you still have this issue ? I just tried a similar design (PLL with output manually connected to a SB_GB) and it works fine here.

It's still not the "right" thing (wasing a buffer instead of using the one dedicated to the PLL), but that should still be working, at least for a led blink.

[cr1901]

@smunaut I still have this issue as of commit 9472b6d (using the first snippet of Verilog code with the manually instantiated SB_GB).

[smunaut]

Just for the record, issue was identified as next-pnr placing the PLL instance in the bottom PLL BEL ... which is not available in that package because it doesn't process the LOCKED attributes from the chipdb.

I have a couple of commits to allow to workaround that and other fixes in my 'work' tree https://github.com/smunaut/nextpnr/tree/ice40_work I'll properly submit those once the PLL global stuff has been reviewed.

[smunaut]

I think this can be closed. Works fine on my tinyfpga BX now.