icetime - 1000020.4ns with UP5k about icestorm

[daveshah1]

The problem is an inferred latch in your ram_test.v, because the decoder doesn't cover all possibilities. Without totally rewriting the decoder, the simplest fix I see is to add an "else" clause as follows (choose your own default value) :

    always @*
    begin
      casez ({c12, c11}) // Depending on memory address, select different RAM blocks.
      2'b00: insn = insn0;
      2'b01: insn = insn1;
      2'b10: insn = insn2;
      2'b11: begin
			if (!c10 & !c9 & !c8) insn = insn3;   // Select the 256x16 blocks
			else if (!c10 & !c9 &  c8) insn = insn4;
			else if (!c10 &  c9 & !c8) insn = insn5;
			else if (!c10 &  c9 &  c8) insn = insn6;
			else if ( c10 & !c9 & !c8) insn = insn7;
			else if ( c10 & !c9 &  c8) insn = insn8;
			else insn = 16'h0000;
			end
	  
      endcase

With the fix you get a timing estimate of 37.25MHz.

[daveshah1]

I will keep the issue open however, as a reminder to myself to add a nicer error message in icetime in this situation.

[cliffordwolf]

the simplest fix I see is to add an "else" clause as follows (choose your own default value)

I'd personally prefer a default assignment in the beginning of the block. something like this:

    always @*
    begin
      insn = 16'bx;
      casez ({c12, c11}) // Depending on memory address, select different RAM blocks.
      2'b00: insn = insn0;
      2'b01: insn = insn1;
      2'b10: insn = insn2;
      2'b11: begin
			if (!c10 & !c9 & !c8) insn = insn3;   // Select the 256x16 blocks
			else if (!c10 & !c9 &  c8) insn = insn4;
			else if (!c10 &  c9 & !c8) insn = insn5;
			else if (!c10 &  c9 &  c8) insn = insn6;
			else if ( c10 & !c9 & !c8) insn = insn7;
			else if ( c10 & !c9 &  c8) insn = insn8;
			end
      endcase
    end

[igor-m]

OMG, a freshman's mistake :) Thanks!
The timing estimates from 32-40MHz based on the seed..

[Zaba]

I get a similar report from icetime (with loop-start, the time starting from ~1000000 ns, etc.) with the following Verilog module:

module repro(clk, out);

input		clk;
output		out;
reg	[8:0]	data;

always @(posedge clk) begin
	if (data == 9'd 10)
		data <= 9'b 0;
	else
		data <= data + 1;
end

assign out = data < 9'd 8;

endmodule

Changing the register width from [8:0] to [7:0] makes the icetime report look normal (Edit: at least when using synth_ice40 -abc9...?). The issue seems to originate from the data < 9'd 8 comparison. I don't see any reports in the Yosys log of any inferred latches or any other abnormalities.

Putting aside the question of whether this is good Verilog, I'd really like to figure out why the icetime report looks the way it does.

Yosys/Nextpnr/icetime output: yosys-nextpnr-icetime.log