Related Issues (20)
- Fix auto-grouping to not create two partitions for the same primary output net
- Warning messages about unused partition inputs
- Report: Partition Overview
- Bug in parsing partitions HOT 1
- Unrelated cells sharing the same name can cause conflicting drivers in an amended partition (triggerd by the default ghdl-yosys-plugin output) HOT 5
- Default partitioning of eqy fails to prove equivalence for circuit containing only "eq" and "neq", but succeeds if output is turned into internal wire HOT 4
- Running eqy can final report error "Argument list too long" HOT 8
- Improve error message when encountering unmapped memories in a partition solved and using SBY
- Invalid JSON generated during partition stage HOT 1
- Widely differing behavior with different standard cell libs (but the same design) HOT 5
- Recode sections are matched against the post-combine gold design but applied to the pre-combine gold design.
- ERROR: syntax error in *.eqy line 1 HOT 2
- eqy stuck in infinite loop with gate design primitives (Xilinx gates) as blackboxes HOT 2
- make: yosys-config: No such file or directory
- Unclear error reporting in the presence of multiple conflicting drivers HOT 11
- Support for UDP? HOT 8
- Make install not working HOT 2
- EQY fails to prove a cell mapping equivalent HOT 3
- Unclear what the error is HOT 3
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from eqy.