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accelerating-cnn-with-fpga

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

am-mobilenet1d

The Additive Margin MobileNet1D is a new light weight deep learning model for Speaker Recognition which is based on the MobileNetV2 architecture and the Additive Margin Softmax (AM-Softmax) loss function.)

cnn-fpga

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

cnn-on-fpga

FPGA

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

e203_hbirdv2

The Ultra-Low Power RISC-V Core

end-to-end-asr-pytorch

This is an open source project (formerly named Listen, Attend and Spell - PyTorch Implementation) for end-to-end ASR implemented with Pytorch, the well known deep learning toolkit.

git-man

Git 使用规范手册

git_test

一生一芯计划

github-slideshow

A robot powered training repository :robot:

handsign-digits-classification-on-zynqmp

hbird-sdk

OpenSource HummingBird RISC-V Software Development Kit

imageprocessing-python

该资源为作者在CSDN的撰写Python图像处理文章的支撑，主要是Python实现图像处理、图像识别、图像分类等算法代码实现，希望该资源对您有所帮助，一起加油。

l-ink_card

Smart NFC & ink-Display Card

lee-nlp_asr2020

主要参考李宏毅老师2020年人类语言处理课程资料整理，包括代码和ppt

numpy-100

100 numpy exercises (with solutions)

nutshell

RISC-V SoC designed by students in UCAS

os_info_display

OS information display system

oscpu-framework

A Verilator-based demo.

pp4fpgas-cn

中文版 Parallel Programming for FPGAs

pynq

Python Productivity for ZYNQ

riscv-dbg

RISC-V Debug Support for our PULP RISC-V Cores

riscv-operating-system-mooc

《从头写一个RISC-V OS》课程配套的资源

runningrobot-scu-2021

The name of our team is Avator. We are SCUers.

snn-simulator-nest_14.0-xilinx_fpga_cluster

A Spiking neural network simulator NEST base on FPGA‘s cluster（LIF NEURON）

sw_machine_learning

machine learning

ultra96-pynq

Board files to build Ultra 96 PYNQ image

vmamba

VMamba: Visual State Space Models，code is based on mamba

wallace

xuan