instruction information about sandsifter

[hlide]

• 0f 18 /4-7: Hintable NOP, See U.S. Patent 5,701,442.
• df c0-c7 : 8087, FREEP st(0-7). See sandpile.org.
• d6 : S(ET)ALC^I64. I64 stands for "invalid in PM64". I know very well this instruction as I used it at 486 times; AL = CF ? 0xFF : 0x00. This instruction was always "unofficial" and so retro-compatibility may not work here.
• dbe0 : FENI only for real coprocessor 8087 - enable interrupt; others - same as FNOP (maintained for 8087 retro-compatibility)
• dbe1 : FDISI only for real coprocessor 8087 - disable interrupt; others - same as FNOP (maintained for 8087 retro-compatibility)
• c[0|1],d[0|1|2|3] : SAL as SHL aliases (maintained for 8086 retro-compatibility). See sandpile.org -- IA-32 architecture -- opcode groups
• f6 /1, f7 /1 : TEST aliases (maintained for 8086 retro-compatibility). Christian Ludloff wrote: "While the latest Intel manuals still omit this de-facto standard, the recent x86-64 manuals from AMD document it".
• f1 : INT1, ICEBP. AMD documents it. Christian Ludloff wrote: "Unlike INT 1 (CDh,01h), INT1 (F1h) doesn't perform the IOPL or DPL check and it can't be redirected via the TSS32.IRB".
• e8, e9 : See sandpile.org. CALL/JMP^Df64 Jz. Df64 stands for "defaults to O64 in PM64; 66h results in O16 in AMD64 but is ignored in EM64T (near branches)".

sandpile.org has a pretty good documentation.

[xoreaxeaxeax]

We may update in the future (sandpile is a useful site) but the goal of the project is really to find instructions that are undocumented by the manufacturer; resolving their functionality is an effort for another day. As for 66 e8/e9 - I believe the paper and slides specify this is for 64 bit code; every Intel processor I've checked discards the prefix in this case, which is not what disassemblers are doing.