Comments (1)
Done. Now, if hdl
parameter is not specified all VHDL files are generated in FuseSoc cache directory. If it is specified, then it is relative path to the foo.core
file.
from agwb.
Related Issues (20)
- Problem with the newest version of GHDL HOT 4
- Better granularity of the version identifiers.
- Detection of incorrect attributes in system description. HOT 1
- Adding the test registers at known address locations. HOT 2
- Validation of system description XML with RelaxNG sometimes gives incorrect error reports HOT 2
- Enabling stb generates incompatible port name. HOT 1
- Using the registered Wishbone crossbar in more complex designs HOT 2
- Current CDC block is inefficient for connecting clock domains using synchronous clocks with different frequencies
- Implementation of the "extended interface" - to make use of the extended features of IPbus, E2bus or CBM DCA - how to implement RMW? HOT 3
- Python backend support vor variants HOT 3
- Selection between "agwb" and "agwb_dca" does not work correctly now. HOT 1
- Mixed usage of "downto" and "to" in indexing in AGWB VHDL code HOT 1
- Mistake in wb_cdc? HOT 3
- Connecting Wishbone busses - naming conventions
- Better handling of BlackBoxes - support for HLS? HOT 9
- Certain problems with RelaxNG syntax validation HOT 1
- Potential problem with constants within block declarations.
- Incorrect code generated when the default value is set in the vector of control registers HOT 1
- Explicit register addresses as constants in HDL package HOT 4
- Automated generation of mutiple registers for width > 32
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